Datasheet

 2013-2014 Microchip Technology Inc. DS70000689D-page 45
dsPIC33EPXXXGM3XX/6XX/7XX
4.2.5 X AND Y DATA SPACES
The dsPIC33EP core has two Data Spaces: X and Y.
These Data Spaces can be considered either separate
(for some DSP instructions) or as one unified linear
address range (for MCU instructions). The Data
Spaces are accessed using two Address Generation
Units (AGUs) and separate data paths. This feature
allows certain instructions to concurrently fetch two
words from RAM, thereby enabling efficient execution
of DSP algorithms, such as Finite Impulse Response
(FIR) filtering and Fast Fourier Transform (FFT).
The X Data Space is used by all instructions and
supports all addressing modes. The X Data Space has
separate read and write data buses. The X read data
bus is the read data path for all instructions that view
Data Space as combined X and Y address space. It is
also the X data prefetch path for the dual operand DSP
instructions (MAC class).
The Y Data Space is used in concert with the X Data
Space by the MAC class of instructions (CLR, ED,
EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to provide
two concurrent data read paths.
Both the X and Y Data Spaces support Modulo
Addressing mode for all instructions, subject to
addressing mode restrictions. Bit-Reversed Addressing
mode is only supported for writes to X Data Space.
All data memory writes, including in DSP instructions,
view Data Space as combined X and Y address space.
The boundary between the X and Y Data Spaces is
device-dependent and is not user-programmable.