Datasheet

 2013-2014 Microchip Technology Inc. DS70000689D-page 449
dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 33-5: POWER-ON RESET TIMING CHARACTERISTICS
VDD
VPOR
Note 1: The power-up period will be extended if the power-up sequence completes before the device exits from
BOR (V
DD < VBOR).
2: The power-up period includes internal voltage regulator stabilization delay.
SY00
Power-up Sequence
V
DD
VPOR
(TPU)
SY10
SY11
Power-up Sequence
(Notes 1,2)
CPU Starts Fetching Code
CPU Starts Fetching Code
(TPWRT)
Power-up Timer Disabled – Clock Sources = (HS, HSPLL, XT and XTPLL)
V
DD
VPOR
SY00
Power-up Sequence
(T
PU)
CPU Starts Fetching Code
(Notes 1,2)
(Notes 1,2)
Power-up Timer Disabled – Clock Sources = (FRC, FRCDIVN, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
Power-up Timer Enabled – Clock Sources = (FRC, FRCDIVN, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
(TOST)
SY00
(T
PU)
VDD
VPOR
Greater of
Power-up Sequence
(Notes 1,2)
CPU Starts Fetching Code
Power-up Timer Enabled – Clock Sources = (HS, HSPLL, XT and XTPLL)
SY00
(T
PU )
SY11 (T PWRT )
SY10 (T
OST )
or