Datasheet

dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 416  2013-2014 Microchip Technology Inc.
30.2 User ID Words
dsPIC33EPXXXGM3XX/6XX/7XX devices contain four
User ID Words, located at addresses, 0x800FF8
through 0x800FFE. The User ID Words can be used for
storing product information, such as serial numbers,
system manufacturing dates, manufacturing lot
numbers and other application-specific information.
The User ID Words register map is shown in
Table 30-3.
TABLE 30-3: USER ID WORDS REGISTER
MAP
30.3 On-Chip Voltage Regulator
All of the dsPIC33EPXXXGM3XX/6XX/7XX devices
power their core digital logic at a nominal 1.8V. This can
create a conflict for designs that are required to operate at
a higher typical voltage, such as 3.3V. To simplify system
design, all devices in the dsPIC33EPXXXGM3XX/6XX/
7XX family incorporate an on-chip regulator that allows
the device to run its core logic from V
DD.
The regulator provides power to the core from the other
V
DD pins. A low-ESR (less than 1 Ohm) capacitor (such
as tantalum or ceramic) must be connected to the V
CAP
pin (Figure 30-1). This helps to maintain the stability of
the regulator. The recommended value for the filter
capacitor is provided in Table 3 3-5, located in
Section 33.0 “Electrical Characteristics”.
FIGURE 30-1: CONNECTIONS FOR THE
ON-CHIP VOLTAGE
REGULATOR
(1,2,3)
30.4 Brown-out Reset (BOR)
The Brown-out Reset (BOR) module is based on an
internal voltage reference circuit that monitors the reg-
ulated supply voltage, V
CAP. The main purpose of the
BOR module is to generate a device Reset when a
brown-out condition occurs. Brown-out conditions are
generally caused by glitches on the AC mains (for
example, missing portions of the AC cycle waveform
due to bad power transmission lines or voltage sags
due to excessive current draw when a large inductive
load is turned on).
A BOR generates a Reset pulse, which resets the
device. The BOR selects the clock source, based on
the device Configuration bit values (FNOSC<2:0> and
POSCMD<1:0>).
If an oscillator mode is selected, the BOR activates the
Oscillator Start-up Timer (OST). The system clock is
held until OST expires. If the PLL is used, the clock is
held until the LOCK bit (OSCCON<5>) is ‘1’.
Concurrently, the Power-up Timer (PWRT) Time-out
(T
PWRT) is applied before the internal Reset is released.
If T
PWRT = 0 and a crystal oscillator is being used, then a
nominal delay of T
FSCM is applied. The total delay in this
case is T
FSCM. Refer to Parameter SY35 in Table 33-21
of Section 33.0 “Electrical Characteristics” for specific
TFSCM values.
The BOR Status bit (RCON<1>) is set to indicate that a
BOR has occurred. The BOR circuit continues to oper-
ate while in Sleep or Idle mode and resets the device
should V
DD fall below the BOR threshold voltage.
File Name Address Bits<23:16> Bits<15:0>
FUID0 0x800FF8
—UID0
FUID1 0x800FFA —UID1
FUID2 0x800FFC —UID2
FUID3 0x800FFE
—UID3
Legend: — = unimplemented, read as ‘1’.
Note: It is important for the low-ESR capacitor to
be placed as close as possible to the V
CAP
pin.
Note 1: These are typical operating voltages. Refer
to Table 33-5 located in Section 33.1 “DC
Characteristics” for the full operating
ranges of V
DD and VCAP.
2: It is important for the low-ESR capacitor to be
placed as close as possible to the V
CAP pin.
3: Typical VCAP pin voltage = 1.8V when
V
DD ≥ VDDMIN.
VDD
VCAP
VSS
dsPIC33EP
3.3V
CEFC