Datasheet

 2013-2014 Microchip Technology Inc. DS70000689D-page 399
dsPIC33EPXXXGM3XX/6XX/7XX
bit 5-2 WAITM<3:0>: Read to Byte Enable Strobe Wait State Configuration bits
1111 = Wait of additional 15 TP
•
•
•
0001 = Wait of additional 1 T
P
0000 = No additional Wait cycles (operation forced into one TP)
bit 1-0 WAITE<1:0>: Data Hold After Strobe Wait State Configuration bits
(1,2,3)
11 = Wait of 4 TP
10 = Wait of 3 TP
01 = Wait of 2 TP
00 = Wait of 1 TP
REGISTER 28-2: PMMODE: PARALLEL MASTER PORT MODE REGISTER
(4)
(CONTINUED)
Note 1: The applied Wait state depends on whether data and address are multiplexed or demultiplexed. See
Section 4.1.8 “Wait States” in the “Parallel Master Port (PMP)” (DS70576) in the “dsPIC33/PIC24
Family Reference Manual” for more information.
2: WAITB<1:0> and WAITE<1:0> bits are ignored whenever WAITM<3:0> = 0000.
3: T
P = 1/FP.
4: This register is not available on 44-pin devices.