Datasheet

dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 398  2013-2014 Microchip Technology Inc.
REGISTER 28-2: PMMODE: PARALLEL MASTER PORT MODE REGISTER
(4)
R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BUSY IRQM1 IRQM0 INCM1 INCM0 MODE16 MODE1 MODE0
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WAITB1
(1,2,3)
WAITB0
(1,2,3)
WAITM3 WAITM2 WAITM1 WAITM0 WAITE1
(1,2,3)
WAITE0
(1,2,3)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at Reset ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 BUSY: Busy bit (Master mode only)
1 = Port is busy
0 = Port is not busy
bit 14-13 IRQM<1:0>: Interrupt Request Mode bits
11 = Interrupt is generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP
mode), or on a read/write operation when PMA<1:0> = 11 (Addressable PSP mode only)
10 = Reserved
01 = Interrupt is generated at the end of the read/write cycle
00 = No Interrupt is generated
bit 12-11 INCM<1:0>: Increment Mode bits
11 = PSP read and write buffers auto-increment (Legacy PSP mode only)
10 = Decrement ADDR by 1 every read/write cycle
01 = Increment ADDR by 1 every read/write cycle
00 = No increment or decrement of address
bit 10 MODE16: 8/16-Bit Mode bit
1 = 16-Bit Mode: Data register is 16 bits, a read/write to the Data register invokes two 8-bit transfers
0 = 8-Bit Mode: Data register is 8 bits, a read/write to the Data register invokes one 8-bit transfer
bit 9-8 MODE<1:0>: Parallel Slave Port Mode Select bits
11 = Master Mode 1 (PMCSx, PMRD/PMWR
, PMENB, PMBE, PMA<x:0> and PMD<7:0>)
10 = Master Mode 2 (PMCSx, PMRD, PMWR, PMBE, PMA<x:0> and PMD<7:0>)
01 = Enhanced PSP, control signals (PMRD, PMWR, PMCSx, PMD<7:0> and PMA<1:0>)
00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCSx and PMD<7:0>)
bit 7-6 WAITB<1:0>: Data Setup to Read/Write/Address Phase Wait State Configuration bits
(1,2,3)
11 = Data Wait of 4 TP (demultiplexed/multiplexed); address phase of 4 TP (multiplexed)
10 = Data Wait of 3 T
P (demultiplexed/multiplexed); address phase of 3 TP (multiplexed)
01 = Data Wait of 2 T
P (demultiplexed/multiplexed); address phase of 2 TP (multiplexed)
00 = Data Wait of 1 T
P (demultiplexed/multiplexed); address phase of 1 TP (multiplexed)
Note 1: The applied Wait state depends on whether data and address are multiplexed or demultiplexed. See
Section 4.1.8 “Wait States” in the “Parallel Master Port (PMP)” (DS70576) in the “dsPIC33/PIC24
Family Reference Manual” for more information.
2: WAITB<1:0> and WAITE<1:0> bits are ignored whenever WAITM<3:0> = 0000.
3: T
P = 1/FP.
4: This register is not available on 44-pin devices.