Datasheet

 2013-2014 Microchip Technology Inc. DS70000689D-page 395
dsPIC33EPXXXGM3XX/6XX/7XX
28.0 PARALLEL MASTER PORT
(PMP)
The Parallel Master Port (PMP) module is a parallel
8-bit I/O module, specifically designed to communi-
cate with a wide variety of parallel devices, such as
communication peripherals, LCDs, external memory
devices and microcontrollers. Because the interface
to parallel peripherals varies significantly, the PMP is
highly configurable.
Key features of the PMP module include:
• Eight Data Lines
• Up to 16 Programmable Address Lines
• Up to 2 Chip Select Lines
• Programmable Strobe Options:
- Individual read and write strobes, or
- Read/Write
strobe with enable strobe
• Address Auto-Increment/Auto-Decrement
• Programmable Address/Data Multiplexing
• Programmable Polarity on Control Signals
• Legacy Parallel Slave Port (PSP) Support
• Enhanced Parallel Slave Support:
- Address support
- 4-byte deep auto-incrementing buffer
• Programmable Wait States
FIGURE 28-1: PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXXGM3XX/6XX/7XX
family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to the “dsPIC33/PIC24 Family
Reference Manual”, “Parallel Master
Port (PMP)” (DS70576), which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
PMA<0>
PMA<14>
PMA<15>
PMBE
PMRD
PMWR
PMD<7:0>
PMENB
PMRD/PMWR
PMCS1
PMA<1>
PMA<13:2>
PMALL
PMALH
PMA<7:0>
PMA<15:8>
PMCS2
EEPROM
Address Bus
Data Bus
Control Lines
dsPIC33EP
LCD
FIFO
Microcontroller
8-Bit Data (with or without multiplexed addressing)
Up to 16-Bit Address
Parallel Master Port
Buffer
Note: Not all PMP port pins are 5V tolerant. Refer to the “Pin Diagrams” section for availability.