Datasheet

dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 386  2013-2014 Microchip Technology Inc.
27.3 RTCC Registers
REGISTER 27-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER
(1)
R/W-0 U-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0
RTCEN
(2)
— RTCWREN RTCSYNC HALFSEC
(3)
RTCOE RTCPTR1 RTCPTR0
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 RTCEN: RTCC Enable bit
(2)
1 = RTCC module is enabled
0 = RTCC module is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 RTCWREN: RTCC Value Register Write Enable bit
1 = RTCVAL register can be written to by the user application
0 = RTCVAL register is locked out from being written to by the user application
bit 12 RTCSYNC: RTCC Value Register Read Synchronization bit
1 = A rollover is about to occur in 32 clock edges (approximately 1 ms)
0 = A rollover will not occur
bit 11 HALFSEC: Half-Second Status bit
(3)
1 = Second half period of a second
0 = First half period of a second
bit 10 RTCOE: RTCC Output Enable bit
1 = RTCC output is enabled
0 = RTCC output is disabled
bit 9-8 RTCPTR<1:0>: RTCC Value Register Pointer bits
Points to the corresponding RTCC Value register when reading the RTCVAL register; the
RTCPTR<1:0> value decrements on every access of the RTCVAL register until it reaches ‘00’.
bit 7-0 CAL<7:0>: RTCC Drift Calibration bits
01111111 = Maximum positive adjustment; adds 508 RTCC clock pulses every one minute
•
•
•
00000001 = Minimum positive adjustment; adds 4 RTCC clock pulses every one minute
00000000 = No adjustment
11111111 = Minimum negative adjustment; subtracts 4 RTCC clock pulses every one minute
•
•
•
10000000 = Maximum negative adjustment; subtracts 512 RTCC clock pulses every one minute
Note 1: The RCFGCAL register is only affected by a POR.
2: A write to the RTCEN bit is only allowed when RTCWREN = 1.
3: This bit is read-only. It is cleared when the lower half of the MINSEC register is written.