Datasheet

 2013-2014 Microchip Technology Inc. DS70000689D-page 379
dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 26-6: CMxFLTR: COMPARATOR x FILTER CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— CFSEL2 CFSEL1 CFSEL0 CFLTREN CFDIV2 CFDIV1 CFDIV0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-7 Unimplemented: Read as ‘0’
bit 6-4 CFSEL<2:0>: Comparator Filter Input Clock Select bits
111 = T5CLK
(1)
110 = T4CLK
(2)
101 = T3CLK
(1)
100 = T2CLK
(2)
011 = SYNCO2
010 = SYNCO1
(3)
001 = FOSC
(4)
000 = FP
(4)
bit 3 CFLTREN: Comparator Filter Enable bit
1 = Digital filter is enabled
0 = Digital filter is disabled
bit 2-0 CFDIV<2:0>: Comparator Filter Clock Divide Select bits
111 = Clock Divide 1:128
110 = Clock Divide 1:64
101 = Clock Divide 1:32
100 = Clock Divide 1:16
011 = Clock Divide 1:8
010 = Clock Divide 1:4
001 = Clock Divide 1:2
000 = Clock Divide 1:1
Note 1: See the Type C Timer Block Diagram (Figure 13-2).
2: See the Type B Timer Block Diagram (Figure 13-1).
3: See the PWMx Module Register Interconnect Diagram (Figure 16-2).
4: See the Oscillator System Diagram (Figure 9-1).