Datasheet

dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 374  2013-2014 Microchip Technology Inc.
bit 7-6 EVPOL<1:0>: Trigger/Event/Interrupt Polarity Select bits
(2)
11 = Trigger/event/interrupt generated on any change of the comparator output (while CEVT = 0)
10 = Trigger/event/interrupt generated only on high-to-low transition of the polarity selected comparator
output (while CEVT = 0)
If CPOL =
1 (inverted polarity):
Low-to-high transition of the comparator output.
If CPOL =
0 (non-inverted polarity):
High-to-low transition of the comparator output.
01 = Trigger/event/interrupt generated only on low-to-high transition of the polarity selected comparator
output (while CEVT = 0)
If CPOL =
1 (inverted polarity):
High-to-low transition of the comparator output.
If CPOL =
0 (non-inverted polarity):
Low-to-high transition of the comparator output.
00 = Trigger/event/interrupt generation is disabled
bit 5 Unimplemented: Read as ‘0’
bit 4 CREF: Comparator Reference Select bit (V
IN+ input)
(1)
1 = VIN+ input connects to internal CVREFIN voltage
0 = V
IN+ input connects to C4IN1+ pin
bit 3-2 Unimplemented: Read as ‘0’
bit 1-0 CCH<1:0>: Comparator Channel Select bits
(1)
11 = VIN- input of comparator connects to OA3/AN6
10 = V
IN- input of comparator connects to OA2/AN0
01 = V
IN- input of comparator connects to OA1/AN3
00 = V
IN- input of comparator connects to C4IN1-
REGISTER 26-3: CM4CON: OP AMP/COMPARATOR 4 CONTROL REGISTER (CONTINUED)
Note 1: Inputs that are selected and not available will be tied to VSS. See the “Pin Diagrams” section for available
inputs for each package.
2: After configuring the comparator, either for a high-to-low or low-to-high COUT transition
(EVPOL<1:0> (CMxCON<7:6>) = 10 or 01), the Comparator Event bit, CEVT (CMxCON<9>), and the
Comparator Combined Interrupt Flag, CMPIF (IFS1<2>), must be cleared before enabling the
Comparator Interrupt Enable bit, CMPIE (IEC1<2>).