Datasheet

 2013-2014 Microchip Technology Inc. DS70000689D-page 371
dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 26-2: CMxCON: OP AMP/COMPARATOR x CONTROL
REGISTER (x = 1, 2, 3 OR 5)
R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0
CON COE CPOL
— —OPMODE
(2)
CEVT
(3)
COUT
bit 15 bit 8
R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0
EVPOL1
(3)
EVPOL0
(3)
—CREF
(1)
— — CCH1
(1)
CCH0
(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CON: Op Amp/Comparator Enable bit
1 = Comparator is enabled
0 = Comparator is disabled
bit 14 COE: Comparator Output Enable bit
1 = Comparator output is present on the CxOUT pin
0 = Comparator output is internal only
bit 13 CPOL: Comparator Output Polarity Select bit
1 = Comparator output is inverted
0 = Comparator output is not inverted
bit 12-11 Unimplemented: Read as ‘0’
bit 10 OPMODE: Op Amp Select bit
(2)
1 = Op amp is enabled
0 = Op amp is disabled
bit 9 CEVT: Comparator Event bit
(3)
1 = Comparator event, according to the EVPOL<1:0> settings, occurred; disables future triggers and
interrupts until the bit is cleared
0 = Comparator event did not occur
bit 8 COUT: Comparator Output bit
When CPOL =
0 (non-inverted polarity):
1 = VIN+ > VIN-
0 = V
IN+ < VIN-
When CPOL = 1 (inverted polarity):
1 = VIN+ < VIN-
0 = V
IN+ > VIN-
Note 1: Inputs that are selected and not available will be tied to V
SS. See the “Pin Diagrams” section for available
inputs for each package.
2: The op amp and the comparator can be used simultaneously in these devices. The OPMODE bit only
enables the op amp while the comparator is still functional.
3: After configuring the comparator, either for a high-to-low or low-to-high COUT transition
(EVPOL<1:0> (CMxCON<7:6>) = 10 or 01), the Comparator Event bit, CEVT (CMxCON<9>), and the
Comparator Combined Interrupt Flag, CMPIF (IFS1<2>), must be cleared before enabling the
Comparator Interrupt Enable bit, CMPIE (IEC1<2>).