Datasheet

dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 368  2013-2014 Microchip Technology Inc.
26.1 Op Amp Application
Considerations
There are two configurations to take into consider-
ation when designing with the op amp modules that
are available in the dsPIC33EPXXXGM3XX/6XX/7XX
devices. Configuration A (see Figure 26-5) takes
advantage of the internal connection to the ADCx
module to route the output of the op amp directly to the
ADCx for measurement. Configuration B (see
Figure 26-6) requires that the designer externally route
the output of the op amp (OAxOUT) to a separate ana-
log input pin (ANy) on the device. Table 33-53 in
Section 33.0 “Electrical Characteristics” describes
the performance characteristics for the op amps, distin-
guishing between the two configuration types where
applicable.
26.1.1 OP AMP CONFIGURATION A
Figure 26-5 shows a typical inverting amplifier circuit
taking advantage of the internal connections from the
op amp output to the input of the ADCx. The advantage
of this configuration is that the user does not need to con-
sume another analog input (ANy) on the device, and
allows the user to simultaneously sample all three
op amps with the ADCx module, if needed. However, the
presence of the internal resistance, R
INT1, adds an error
in the feedback path. Since R
INT1 is an internal resis-
tance, in relation to the op amp output (V
OAxOUT) and
ADCx internal connection (V
ADC), RINT1 must be
included in the numerator term of the transfer function.
See Table 33-52 in Section 33.0 “Electrical Character-
istics” for the typical value of R
INT1. Table 33-57 and
Table 33-58 in Section 33.0 “Electrical Characteris-
tics” describe the minimum sample time (T
SAMP)
requirements for the ADCx module in this configuration.
Figure 26-5 also defines the equations that should be
used when calculating the expected voltages at points,
V
ADC and VOAXOUT.
FIGURE 26-5: OP AMP CONFIGURATION A
–
+
CxIN1-
CxIN1+
R
1
ADCx
(3)
OAxOUT
R
INT1
(1)
RFEEDBACK
(2)
OAx
(to ADCx)
Op Amp x
Note 1: See Table 33-56 for the Typical value.
2: See Table 33-52 for the Minimum value for the feedback resistor.
3: See Table 33-59 and Table 33-60 for the Minimum Sample Time (T
SAMP).
4: CVREF1O or CVREF2O are two options that are available for supplying bias voltage to the op amps.
V
IN
VADC
(VOAXOUT)
V
OAxOUT
R
FEEDBACK
R
1
------------------------------


Bias Voltage V–
IN
=
V
ADC
R
FEEDBACK
R
INT1
+
R
1
---------------------------------------------------


Bias Voltage V–
IN
=
Bias
Voltage
(4)