Datasheet

dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 344  2013-2014 Microchip Technology Inc.
24.2 DCI Control Registers
REGISTER 24-1: DCICON1: DCI CONTROL REGISTER 1
R/W-0 r-0 R/W-0 r-0 R/W-0 R/W-0 R/W-0 R/W-0
DCIEN r DCISIDL r DLOOP CSCKD CSCKE COFSD
bit 15 bit 8
R/W-0 R/W-0 R/W-0 r-0 r-0 r-0 R/W-0 R/W-0
UNFM CSDOM DJST r r r COFSM1 COFSM0
bit 7 bit 0
Legend: r = Reserved bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 DCIEN: DCI Module Enable bit
1 = DCI module is enabled
0 = DCI module is disabled
bit 14 Reserved: Read as ‘0’
bit 13 DCISIDL: DCI Stop in Idle Control bit
1 = Module will halt in CPU Idle mode
0 = Module will continue to operate in CPU Idle mode
bit 12 Reserved: Read as ‘0’
bit 11 DLOOP: Digital Loopback Mode Control bit
1 = Digital Loopback mode is enabled; CSDI and CSDO pins are internally connected
0 = Digital Loopback mode is disabled
bit 10 CSCKD: Sample Clock Direction Control bit
1 = CSCK pin is an input when DCI module is enabled
0 = CSCK pin is an output when DCI module is enabled
bit 9 CSCKE: Sample Clock Edge Control bit
1 = Data changes on serial clock falling edge, sampled on serial clock rising edge
0 = Data changes on serial clock rising edge, sampled on serial clock falling edge
bit 8 COFSD: Frame Synchronization Direction Control bit
1 = COFS pin is an input when DCI module is enabled
0 = COFS pin is an output when DCI module is enabled
bit 7 UNFM: Underflow Mode bit
1 = Transmits last value written to the Transmit registers on a transmit underflow
0 = Transmits ‘0’s on a transmit underflow
bit 6 CSDOM: Serial Data Output Mode bit
1 = CSDO pin will be tri-stated during disabled transmit time slots
0 = CSDO pin drives ‘0’s during disabled transmit time slots
bit 5 DJST: DCI Data Justification Control bit
1 = Data transmission/reception is begun during the same serial clock cycle as the frame synchronization pulse
0 = Data transmission/reception is begun one serial clock cycle after the frame synchronization pulse
bit 4-2 Reserved: Read as ‘0’
bit 1-0 COFSM<1:0>: Frame Sync Mode bits
11 = 20-Bit AC-Link mode
10 = 16-Bit AC-Link mode
01 = I
2
S Frame Sync mode
00 = Multi-Channel Frame Sync mode