Datasheet

 2013-2014 Microchip Technology Inc. DS70000689D-page 337
dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 23-5: ADxCHS123: ADCx INPUT CHANNEL 1, 2, 3 SELECT REGISTER
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — CH123SB2 CH123SB1 CH123NB1 CH123NB0 CH123SB0
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — CH123SA2 CH123SA1 CH123NA1 CH123NA0 CH123SA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12-11 CH123SB<2:1>: Channels 1, 2, 3 Positive Input Select for Sample B bits
1xx = CH1 positive input is AN0 (Op Amp 2), CH2 positive input is AN25 (Op Amp 5), CH3 positive
input is AN6 (Op Amp 3)
011 = CH1 positive input is AN3 (Op Amp 1), CH2 positive input is AN0 (Op Amp 2), CH3 positive input
is AN25 (Op Amp 5)
010 = CH1 positive input is AN3 (Op Amp 1), CH2 positive input is AN0 (Op Amp 2), CH3 positive input
is AN6 (Op Amp 3)
001 = CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5
000 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2
bit 10-9 CH123NB<1:0>: Channels 1, 2, 3 Negative Input Select for Sample B bits
11 = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11
10 = CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8
0x = CH1, CH2, CH3 negative input is V
REFL
(1)
bit 8 CH123SB0: Channels 1, 2, 3 Positive Input Select for Sample B bit
See bits<12:11> for bit selections.
bit 7-5 Unimplemented: Read as ‘0’
bit 4-3 CH123SA<2:1>: Channels 1, 2, 3 Positive Input Select for Sample A bits
1xx = CH1 positive input is AN0 (Op Amp 2), CH2 positive input is AN25 (Op Amp 5), CH3 positive
input is AN6 (Op Amp 3)
011 = CH1 positive input is AN3 (Op Amp 1), CH2 positive input is AN0 (Op Amp 2), CH3 positive input
is AN25 (Op Amp 5)
010 = CH1 positive input is AN3 (Op Amp 1), CH2 positive input is AN0 (Op Amp 2), CH3 positive input
is AN6 (Op Amp 3)
001 = CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5
000 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2
bit 2-1 CH123NA<1:0>: Channels 1, 2, 3 Negative Input Select for Sample A bits
11 = CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11
10 = CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8
0x = CH1, CH2, CH3 negative input is V
REFL
bit 0 CH123SA0: Channels 1, 2, 3 Positive Input Select for Sample A bit
See bits<4:3> for the bit selections.
Note 1: The negative input to V
REFL happens only when VCFG<2:0> = 2 or 3 in the ADxCON2 register. When
VCFG<2:0> = 0 or 1, this negative input is internally routed to AV
SS.