Datasheet

dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 334  2013-2014 Microchip Technology Inc.
bit 6-2 SMPI<4:0>: Increment Rate bits
When ADDMAEN = 0:
x1111 = Generates interrupt after completion of every 16th sample/conversion operation
x1110 = Generates interrupt after completion of every 15th sample/conversion operation
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x0001 = Generates interrupt after completion of every 2nd sample/conversion operation
x0000 = Generates interrupt after completion of every sample/conversion operation
When ADDMAEN =
1:
11111 = Increments the DMA address after completion of every 32nd sample/conversion operation
11110 = Increments the DMA address after completion of every 31st sample/conversion operation
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00001 = Increments the DMA address after completion of every 2nd sample/conversion operation
00000 = Increments the DMA address after completion of every sample/conversion operation
bit 1 BUFM: Buffer Fill Mode Select bit
1 = Starts buffer filling the first half of the buffer on the first interrupt and the second half of the buffer
on the next interrupt
0 = Always starts filling the buffer from the Start address
bit 0 ALTS: Alternate Input Sample Mode Select bit
1 = Uses channel input selects for Sample MUXA on the first sample and Sample MUXB on the next sample
0 = Always uses channel input selects for Sample MUXA
REGISTER 23-2: ADxCON2: ADCx CONTROL REGISTER 2 (CONTINUED)
Note 1: The ‘001’, ‘010’ and ‘011’ bit combinations for VCFG<2:0> are not applicable on ADC2.
2: ADC2 does not support external V
REF± inputs.