Datasheet

 2013-2014 Microchip Technology Inc. DS70000689D-page 333
dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 23-2: ADxCON2: ADCx CONTROL REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
VCFG2
(1)
VCFG1
(1)
VCFG0
(1)
OFFCAL — CSCNA CHPS1 CHPS0
bit 15 bit 8
R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BUFS SMPI4 SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 VCFG<2:0>: Converter Voltage Reference Configuration bits
(1)
bit 12 OFFCAL: Offset Calibration Mode Select bit
1 = + and – inputs of channel Sample-and-Hold are connected to AVSS
0 = + and – inputs of channel Sample-and-Hold are normal
bit 11 Unimplemented: Read as ‘0’
bit 10 CSCNA: Input Scan Select bit
1 = Scans inputs for CH0+ during Sample MUXA
0 = Does not scan inputs
bit 9-8 CHPS<1:0>: Channel Select bits
In 12-Bit Mode (AD
12B = 1), CHPS<1:0> Bits are Unimplemented and are Read as ‘00’:
1x = Converts CH0, CH1, CH2 and CH3
01 = Converts CH0 and CH1
00 = Converts CH0
bit 7 BUFS: Buffer Fill Status bit (only valid when BUFM = 1)
1 = ADCx is currently filling the second half of the buffer; the user application should access data in
the first half of the buffer
0 = ADCx is currently filling the first half of the buffer; the user application should access data in the
second half of the buffer
Note 1: The ‘001’, ‘010’ and ‘011’ bit combinations for VCFG<2:0> are not applicable on ADC2.
2: ADC2 does not support external V
REF± inputs.
Value VREFH VREFL
000 AVDD AVSS
001 External VREF+
(2)
AVSS
010 AVDD External VREF-
(2)
011 External VREF+
(2)
External VREF-
(2)
1xx AVDD AVSS