Datasheet

dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 332  2013-2014 Microchip Technology Inc.
bit 7-5 SSRC<2:0>: Sample Clock Source Select bits
If SSRCG = 1:
111 = Reserved
110 = PTGO15 primary trigger compare ends sampling and starts conversion
(1)
101 = PTGO14 primary trigger compare ends sampling and starts conversion
(1)
100 = PTGO13 primary trigger compare ends sampling and starts conversion
(1)
011 = PTGO12 primary trigger compare ends sampling and starts conversion
(1)
010 = PWM Generator 3 primary trigger compare ends sampling and starts conversion
001 = PWM Generator 2 primary trigger compare ends sampling and starts conversion
000 = PWM Generator 1 primary trigger compare ends sampling and starts conversion
If SSRCG =
0:
111 = Internal counter ends sampling and starts conversion (auto-convert)
110 = CTMU ends sampling and starts conversion
101 = PWM secondary Special Event Trigger ends sampling and starts conversion
100 = Timer5 compare ends sampling and starts conversion
011 = PWM primary Special Event Trigger ends sampling and starts conversion
010 = Timer3 compare ends sampling and starts conversion
001 = Active transition on the INT0 pin ends sampling and starts conversion
000 = Clearing the Sample bit (SAMP) ends sampling and starts conversion (Manual mode)
bit 4 SSRCG: Sample Trigger Source Group bit
See SSRC<2:0> for details.
bit 3 SIMSAM: Simultaneous Sample Select bit (only applicable when CHPS<1:0> = 01 or 1x)
In 12-Bit Mode (AD12B =
1), SIMSAM is Unimplemented and is Read as ‘0’:
1 = Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x), or samples CH0 and CH1
simultaneously (when CHPS<1:0> = 01)
0 = Samples multiple channels individually in sequence
bit 2 ASAM: ADCx Sample Auto-Start bit
1 = Sampling begins immediately after last conversion; SAMP bit is auto-set
0 = Sampling begins when SAMP bit is set
bit 1 SAMP: ADCx Sample Enable bit
1 = ADCx Sample-and-Hold amplifiers are sampling
0 = ADCx Sample-and-Hold amplifiers are holding
If ASAM = 0, software can write ‘1’ to begin sampling. Automatically set by hardware if ASAM = 1. If
SSRC<2:0> = 000, software can write ‘0’ to end sampling and start conversion. If SSRC<2:0> 000,
automatically cleared by hardware to end sampling and start conversion.
bit 0 DONE: ADCx Conversion Status bit
(2)
1 = ADCx conversion cycle is completed.
0 = ADCx conversion has not started or is in progress
Automatically set by hardware when A/D conversion is complete. Software can write ‘0’ to clear DONE
status (software not allowed to write ‘1’). Clearing this bit does NOT affect any operation in progress.
Automatically cleared by hardware at the start of a new conversion.
REGISTER 23-1: ADxCON1: ADCx CONTROL REGISTER 1 (CONTINUED)
Note 1: See Section 25.0 “Peripheral Trigger Generator (PTG) Module” for information on this selection.
2: Do not clear the DONE bit in software if ADCx Sample Auto-Start bit is enabled (ASAM = 1).