Datasheet

dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 330  2013-2014 Microchip Technology Inc.
23.2 ADCx Helpful Tips
1. The SMPIx control bits in the ADxCON2 registers:
a) Determine when the ADCx interrupt flag is
set and an interrupt is generated, if
enabled.
b) When the CSCNA bit in the ADxCON2 reg-
ister is set to ‘1’, this determines when the
ADCx analog scan channel list, defined in
the AD1CSSL/AD1CSSH registers, starts
over from the beginning.
c) When the DMA peripheral is not used
(ADDMAEN = 0), this determines when the
ADCx Result Buffer Pointer to ADC1BUF0-
ADC1BUFF gets reset back to the
beginning at ADC1BUF0.
d) When the DMA peripheral is used
(ADDMAEN = 1), this determines when the
DMA Address Pointer is incremented after a
sample/conversion operation. ADC1BUF0 is
the only ADCx buffer used in this mode. The
ADCx Result Buffer Pointer to ADC1BUF0-
ADC1BUFF gets reset back to the beginning
at ADC1BUF0. The DMA address is incre-
mented after completion of every 32nd
sample/conversion operation. Conversion
results are stored in the ADC1BUF0
register for transfer to RAM using the DMA
peripheral.
2. When the DMA module is disabled
(ADDMAEN = 0), the ADCx has 16 result buffers.
ADCx conversion results are stored sequentially
in ADC1BUF0-ADC1BUFF, regardless of which
analog inputs are being used subject to the SMPIx
bits and the condition described in 1.c) above.
There is no relationship between the ANx input
being measured and which ADCx buffer
(ADC1BUF0-ADC1BUFF) that the conversion
results will be placed in.
3. When the DMA module is enabled
(ADDMAEN = 1), the ADCx module has only
1 ADCx result buffer (i.e., ADC1BUF0) per
ADCx peripheral and the ADCx conversion
result must be read, either by the CPU or DMA
Controller, before the next ADCx conversion is
complete to avoid overwriting the previous
value.
4. The DONE bit (ADxCON1<0>) is only cleared at
the start of each conversion and is set at the
completion of the conversion, but remains set
indefinitely, even through the next sample phase
until the next conversion begins. If application
code is monitoring the DONE bit in any kind of
software loop, the user must consider this
behavior because the CPU code execution is
faster than the ADCx. As a result, in Manual
Sample mode, particularly where the user’s
code is setting the SAMP bit (ADxCON1<1>),
the DONE bit should also be cleared by the user
application just before setting the SAMP bit.
5. Enabling op amps, comparator inputs and exter-
nal voltage references can limit the availability of
analog inputs (ANx pins). For example, when
Op Amp 2 is enabled, the pins for AN0, AN1 and
AN2 are used by the op amp’s inputs and output.
This negates the usefulness of Alternate Input
mode since the MUXA selections use AN0-AN2.
Carefully study the ADCx block diagram to deter-
mine the configuration that will best suit your
application. Configuration examples are available
in the “dsPIC33/PIC24 Family Reference
Manual”, “Analog-to-Digital Converter (ADC)”
(DS70621)