Datasheet

 2013-2014 Microchip Technology Inc. DS70000689D-page 323
dsPIC33EPXXXGM3XX/6XX/7XX
22.1 CTMU Control Registers
REGISTER 22-1: CTMUCON1: CTMU CONTROL REGISTER 1
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CTMUEN
— CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN
(1)
CTTRIG
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CTMUEN: CTMU Enable bit
1 = Module is enabled
0 = Module is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 CTMUSIDL: CTMU Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12 TGEN: Time Generation Enable bit
1 = Enables edge delay generation
0 = Disables edge delay generation
bit 11 EDGEN: Edge Enable bit
1 = Hardware modules are used to trigger edges (TMRx, CTEDx, etc.)
0 = Software is used to trigger edges (manual set of EDGxSTAT)
bit 10 EDGSEQEN: Edge Sequence Enable bit
1 = Edge 1 event must occur before Edge 2 event can occur
0 = No edge sequence is needed
bit 9 IDISSEN: Analog Current Source Control bit
(1)
1 = Analog current source output is grounded
0 = Analog current source output is not grounded
bit 8 CTTRIG: ADCx Trigger Control bit
1 = CTMU triggers ADCx start of conversion
0 = CTMU does not trigger ADCx start of conversion
bit 7-0 Unimplemented: Read as ‘0’
Note 1: The ADCx module Sample-and-Hold (S&H) capacitor is not automatically discharged between
sample/conversion cycles. Any software using the ADCx as part of a capacitance measurement must
discharge the ADCx capacitor before conducting the measurement. The IDISSEN bit, when set to ‘1’, per-
forms this function. The ADCx must be sampling while the IDISSEN bit is active to connect the discharge
sink to the capacitor array.