Datasheet

 2013-2014 Microchip Technology Inc. DS70000689D-page 311
dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 21-19: CxFMSKSEL2: CAN x FILTERS 15-8 MASK SELECTION REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
F15MSK1 F15MSK0 F14MSK1 F14MSK0 F13MSK1 F13MSK0 F12MSK1 F12MSK0
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
F11MSK1 F11MSK0 F10MSK1 F10MSK0 F9MSK1 F9MSK0 F8MSK1 F8MSK0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 F15MSK<1:0>: Mask Source for Filter 15 bit
11 = Reserved
10 = Acceptance Mask 2 registers contain mask
01 = Acceptance Mask 1 registers contain mask
00 = Acceptance Mask 0 registers contain mask
bit 13-12 F14MSK<1:0>: Mask Source for Filter 14 bit (same values as bits 15-14)
bit 11-10 F13MSK<1:0>: Mask Source for Filter 13 bit (same values as bits 15-14)
bit 9-8 F12MSK<1:0>: Mask Source for Filter 12 bit (same values as bits 15-14)
bit 7-6 F11MSK<1:0>: Mask Source for Filter 11 bit (same values as bits 15-14)
bit 5-4 F10MSK<1:0>: Mask Source for Filter 10 bit (same values as bits 15-14)
bit 3-2 F9MSK<1:0>: Mask Source for Filter 9 bit (same values as bits 15-14)
bit 1-0 F8MSK<1:0>: Mask Source for Filter 8 bit (same values as bits 15-14)