Datasheet

 2013-2014 Microchip Technology Inc. DS70000689D-page 281
dsPIC33EPXXXGM3XX/6XX/7XX
19.0 INTER-INTEGRATED
CIRCUIT™ (I
2
C™)
The dsPIC33EPXXXGM3XX/6XX/7XX family of
devices contains two Inter-Integrated Circuit (I
2
C)
modules: I2C1 and I2C2.
The I
2
C module provides complete hardware support
for both Slave and Multi-Master modes of the I
2
C serial
communication standard, with a 16-bit interface.
The I
2
C module has a 2-pin interface:
• The SCLx pin is clock.
• The SDAx pin is data.
The I
2
C module offers the following key features:
•I
2
C Interface Supporting both Master and Slave
modes of Operation.
•I
2
C Slave mode Supports 7 and
10-Bit Addressing.
•I
2
C Master mode Supports 7 and
10-Bit Addressing.
•I
2
C Port Allows Bidirectional Transfers Between
Master and Slaves.
• Serial Clock Synchronization for I
2
C Port can be
used as a Handshake Mechanism to Suspend
and Resume Serial Transfer (SCLREL control).
•I
2
C Supports Multi-Master Operation, Detects Bus
Collision and Arbitrates Accordingly.
• Intelligent Platform Management Interface (IPMI)
Support
• System Management Bus (SMBus) Support
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXXGM3XX/6XX/7XX
family of devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to the “dsPIC33/PIC24 Family
Reference Manual”, “Inter-Integrated
Circuit™ (I
2
C™)” (DS70000195), which
is available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.