Datasheet

dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 28  2013-2014 Microchip Technology Inc.
FIGURE 3-1: dsPIC33EPXXXGM3XX/6XX/7XX CPU BLOCK DIAGRAM
Instruction
Decode and
Control
16
PCH
16
Program Counter
16-Bit ALU
24
24
24
24
X Data Bus
PCU
16
16
16
Divide
Support
Engine
DSP
ROM Latch
16
Y Data Bus
EA MUX
X RAGU
X WAGU
Y AGU
16
24
16
16
16
16
16
16
16
8
Interrupt
Controller
PSV and Table
Data Access
Control Block
Stack
Control
Logic
Loop
Control
Logic
Data LatchData Latch
Y Data
RAM
X Data
RAM
Address
Latch
Address
Latch
16
Data Latch
16
16
16
X Address Bus
Y Address Bus
24
Literal Data
Program Memory
Address Latch
Power, Reset
and Oscillator
Control Signals
to Various Blocks
Ports
Peripheral
Modules
Modules
PCL
16 x 16
W Register Array
IR