Datasheet

 2013-2014 Microchip Technology Inc. DS70000689D-page 277

dsPIC33EPXXXGM3XX/6XX/7XX

bit 1 SPITBF: SPIx Transmit Buffer Full Status bit

1 = Transmit has not yet started, SPIxTXB is full

0 = Transmit has started, SPIxTXB is empty

Standard Buffer Mode:

Automatically set in hardware when the core writes to the SPIxBUF location, loading SPIxTXB.

Automatically cleared in hardware when the SPIx module transfers data from SPIxTXB to SPIxSR.

Enhanced Buffer Mode:

Automatically set in hardware when the CPU writes to the SPIxBUF location, loading the last available

buffer location. Automatically cleared in hardware when a buffer location is available for a CPU write

operation.

bit 0 SPIRBF: SPIx Receive Buffer Full Status bit

1 = Receive is complete, SPIxRXB is full

0 = Receive is incomplete, SPIxRXB is empty

Standard Buffer Mode:

Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically

cleared in hardware when the core reads the SPIxBUF location, reading SPIxRXB.

Enhanced Buffer Mode:

Automatically set in hardware when SPIx transfers data from SPIxSR to the buffer, filling the last

unread buffer location. Automatically cleared in hardware when a buffer location is available for a

transfer from SPIxSR.