Datasheet
2013-2014 Microchip Technology Inc. DS70000689D-page 275
dsPIC33EPXXXGM3XX/6XX/7XX
18.1 SPI Helpful Tips
1. In Frame mode, if there is a possibility that the
master may not be initialized before the slave:
a) If FRMPOL (SPIxCON2<13>) = 1, use a
pull-down resistor on SSx
.
b) If FRMPOL = 0, use a pull-up resistor on
SSx
.
2. In Non-Framed 3-Wire mode (i.e., not using SSx
from a master):
a) If CKP (SPIxCON1<6>) = 1, always place a
pull-up resistor on SSx
.
b) If CKP = 0, always place a pull-down
resistor on SSx
.
3. FRMEN (SPIxCON2<15>) = 1 and SSEN
(SPIxCON1<7>) = 1 are exclusive and invalid.
In Frame mode, SCKx is continuous and the
Frame Sync pulse is active on the SSx
pin,
which indicates the start of a data frame.
4. In Master mode only, set the SMP bit
(SPIxCON1<9>) to a ‘1’ for the fastest SPI data
rate possible. The SMP bit can only be set at the
same time or after the MSTEN bit
(SPIxCON1<5>) is set.
To avoid invalid slave read data to the master, the
user’s master software must ensure enough time for
slave software to fill its write buffer before the user
application initiates a master write/read cycle. It is
always advisable to preload the SPIxBUF Transmit
register in advance of the next master transaction
cycle. SPIxBUF is transferred to the SPIx Shift register
and is empty once the data transmission begins.
Note: This insures that the first frame transmis-
sion after initialization is not shifted or
corrupted.
Note: This will insure that during power-up and
initialization, the master/slave will not lose
sync due to an errant SCK transition that
would cause the slave to accumulate data
shift errors, for both transmit and receive,
appearing as corrupted data.
Note: Not all third-party devices support Frame
mode timing. Refer to the SPIx
specifications in Section 33.0 “Electrical
Characteristics” for details.