Datasheet

dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 274  2013-2014 Microchip Technology Inc.
FIGURE 18-1: SPIx MODULE BLOCK DIAGRAM
Internal Data Bus
SDIx
SDOx
SSx
/FSYNCx
SCKx
bit 0
Shift Control
Edge
Select
F
P
Primary
1:1/4/16/64
Enable
Prescaler
Sync
SPIxBUF
Control
Transfer
Transfer
Write SPIxBUF
Read SPIxBUF
16
SPIxCON1<1:0>
SPIxCON1<4:2>
Master Clock
Note 1: In Standard mode, the FIFO is only one level deep.
Clock
Control
8-Level FIFO
Receive Buffer
(1)
SPIxSR
8-Level FIFO
Transmit Buffer
(1)
Secondary
Prescaler
1:1 to 1:8