Datasheet

 2013-2014 Microchip Technology Inc. DS70000689D-page 215
dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 13-3: TYPE B/TYPE C TIMER PAIR BLOCK DIAGRAM (32-BIT TIMER)
TGATE
TCS
00
10
x1
Comparator
TGATE
Set TyIF Flag
(4)
0
1
Equal
Reset
TxCK
(3)
TCKPS<1:0>
F P
(1)
TCKPS<1:0>
Note 1: FP is the peripheral clock.
2: The ADC
X trigger is available only on the TMR3:TMR2 andTMR5:TMR4 32-bit timer pairs.
3: Timerx is a Type B timer (x = 2 and 4).
4: Timery is a Type C timer (x = 3 and 5).
Data
CLK
ADCx
(2)
PRx
(3)
TMRyHLD
(4)
Data Bus<15:0>
mswlsw
Prescaler
(/n)
Prescaler
(/n)
Sync
Gate
Sync
Falling Edge
Detect
PRy
(4)
TMRx
(3)
TCKPS<1:0>
Latch
TMRy
(4)