Datasheet

dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 214  2013-2014 Microchip Technology Inc.
FIGURE 13-1: TYPE B TIMER BLOCK DIAGRAM (x = 2, 4, 6 AND 8)
FIGURE 13-2: TYPE C TIMER BLOCK DIAGRAM (x = 3, 5, 7 AND 9)
Note 1: FP is the peripheral clock.
TGATE
TCS
00
10
x1
PRx
TGATE
Set TxIF Flag
0
1
Equal
Reset
TxCK
TCKPS<1:0>
Gate
Sync
F
P
(1)
Falling Edge
Detect
TCKPS<1:0>
Latch
Data
CLK
TxCLK
TMRx
Comparator
Prescaler
(/n)
Prescaler
(/n)
Sync
Note 1: FP is the peripheral clock.
2: The ADCx trigger is available on TMR3 and TMR5 only.
TGATE
TCS
00
10
x1
PRx
TGATE
Set TxIF Flag
0
1
Equal
Reset
TxCK
TCKPS<1:0>
Gate
Sync
F
P
(1)
Falling Edge
Detect
TCKPS<1:0>
Latch
Data
CLK
TxCLK
TMRx
Comparator
Prescaler
(/n)
Prescaler
(/n)
Sync
ADCx Start of
Conversion
Trigger
(2)