Datasheet

 2013-2014 Microchip Technology Inc. DS70000689D-page 213
dsPIC33EPXXXGM3XX/6XX/7XX
13.0 TIMER2/3, TIMER4/5, TIMER6/7
AND TIMER8/9
The Timer2/3, Timer4/5, Timer6/7 and Timer8/9
modules are 32-bit timers, which can also be
configured as eight independent 16-bit timers with
selectable operating modes.
As a 32-bit timer, Timer2/3, Timer4/5, Timer6/7 and
Timer8/9 operate in three modes:
• Two Independent 16-Bit Timers (e.g., Timer2 and
Timer3) with All 16-Bit Operating modes (except
Asynchronous Counter mode)
• Single 32-Bit Timer
• Single 32-Bit Synchronous Counter
They also support these features:
• Timer Gate Operation
• Selectable Prescaler Settings
• Timer Operation during Idle and Sleep modes
• Interrupt on a 32-Bit Period Register Match
• Time Base for Input Capture and Output Compare
modules
• ADC1 Event Trigger (Timer2/3 only)
Individually, all eight of the 16-bit timers can function as
synchronous timers or counters. They also offer the
features listed previously, except for the event trigger;
this is implemented only with Timer2/3. The operating
modes and enabled features are determined by setting
the appropriate bit(s) in the T2CON, T3CON, T4CON,
T5CON, T6CON, T7CON, T8CON and T9CON regis-
ters. T2CON, T4CON, T6CON and T8CON are shown
in generic form in Register 13-1. T3CON, T5CON,
T7CON and T9CON are shown in Register 13-2.
For 32-bit timer/counter operation, Timer2, Timer4,
Timer6 and Timer8 are the least significant word (lsw);
Timer3, Timer5, Timer7 and Timer9 are the most
significant word (msw) of the 32-bit timers.
A block diagram for an example of a 32-bit timer pair
(Timer2/3 and Timer4/5) is shown in Figure 13-3.
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXXGM3XX/6XX/7XX
family of devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to the “dsPIC33/PIC24 Family
Reference Manual”, “Timers” (DS70362),
which is available from the Microchip
web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Note: For 32-bit operation, T3CON, T5CON,
T7CON and T9CON register control bits
are ignored. Only T2CON, T4CON,
T6CON and T8CON register control bits
are used for setup and control. Timer2,
Timer4, Timer6 and Timer8 clock and gate
inputs are utilized for the 32-bit timer
modules, but an interrupt is generated
with the Timer3, Timer5, Timer7 and
Timer9 interrupt flags.
Note: Only Timer2, 3, 4 and 5 can trigger a DMA
data transfer.