Datasheet

 2013-2014 Microchip Technology Inc. DS70000689D-page 19
dsPIC33EPXXXGM3XX/6XX/7XX
PMA0
PMA1
PMA2-PMA13
PMBE
PMCS1, PMCS2
PMD0-PMD7
PMRD
PMWR
I/O
I/O
O
O
O
I/O
O
O
TTL/ST
TTL/ST
—
—
—
TTL/ST
—
—
No
No
No
No
No
No
No
No
Parallel Master Port Address Bit 0 input (Buffered Slave modes) and
output (Master modes).
Parallel Master Port Address Bit 1 input (Buffered Slave modes) and
output (Master modes).
Parallel Master Port Address Bits 2-13 (Demultiplexed Master modes).
Parallel Master Port Byte Enable strobe.
Parallel Master Port Chip Select 1 and 2 strobe.
Parallel Master Port Data (Demultiplexed Master mode) or
Address/Data (Multiplexed Master modes).
Parallel Master Port Read strobe.
Parallel Master Port Write strobe.
FLT1-FLT2
(1)
FLT3-FLT8
(1)
FLT32
DTCMP1-DTCMP6
(1)
PWM1L-PWM6L
(1)
PWM1H-PWM6H
(1)
SYNCI1
(1)
, SYNCI2
(1)
SYNCO1, SYNCO2
(1)
I
I
I
I
O
O
I
O
ST
ST
ST
ST
—
—
ST
—
Yes
No
No
Yes
No
No
Yes
Yes
PWMx Fault Inputs 1 through 2.
PWMx Fault Inputs 3 through 8
PWMx Fault Input 32
PWMx Dead-Time Compensation Inputs 1 through 6.
PWMx Low Outputs 1 through 7.
PWMx High Outputs 1 through 7.
PWMx Synchronization Input 1.
PWMx Synchronization Outputs 1 and 2.
PGED1
PGEC1
PGED2
PGEC2
PGED3
PGEC3
I/O
I
I/O
I
I/O
I
ST
ST
ST
ST
ST
ST
No
No
No
No
No
No
Data I/O pin for Programming/Debugging Communication Channel 1.
Clock input pin for Programming/Debugging Communication Channel 1.
Data I/O pin for Programming/Debugging Communication Channel 2.
Clock input pin for Programming/Debugging Communication Channel 2.
Data I/O pin for Programming/Debugging Communication Channel 3.
Clock input pin for Programming/Debugging Communication Channel 3.
MCLR
I/P ST No Master Clear (Reset) input. This pin is an active-low Reset to the
device.
AV
DD
(2)
P P No Positive supply for analog modules. This pin must be connected at all
times.
AV
SS P P No Ground reference for analog modules.
V
DD P — No Positive supply for peripheral logic and I/O pins.
VCAP P — No CPU logic filter capacitor connection.
VSS P — No Ground reference for logic and I/O pins.
V
REF+ I Analog No Analog voltage reference (high) input.
VREF- I Analog No Analog voltage reference (low) input.
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Type
Buffer
Type
PPS Description
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
PPS = Peripheral Pin Select TTL = TTL input buffer
Note 1: This pin is not available on all devices. For more information, see the “Pin Diagrams” section for pin
availability.
2: AV
DD must be connected at all times.