Datasheet

dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 186  2013-2014 Microchip Technology Inc.
REGISTER 11-12: RPINR16: PERIPHERAL PIN SELECT INPUT REGISTER 16
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— QEB2R<6:0>
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— QEA2R<6:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-8 QEB2R<6:0>: Assign QEI2 Phase B (QEB2) to the Corresponding RPn/RPIn Pin bits
(see Table 11-2 for input pin selection numbers)
1111111 = Input tied to RP127
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to V
SS
bit 7 Unimplemented: Read as ‘0’
bit 6-0 QEA2R<6:0>: Assign A QEI2 Phase A (QEA2) to the Corresponding RPn/RPIn Pin bits
(see Table 11-2 for input pin selection numbers)
1111111 = Input tied to RP127
•
•
•
0000001 = Input tied to CMP1
0000000 = Input tied to V
SS