Datasheet

dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 164  2013-2014 Microchip Technology Inc.
11.1.1 OPEN-DRAIN CONFIGURATION
In addition to the PORTx, LATx and TRISx registers
for data control, port pins can also be individually
configured for either digital or open-drain output. This
is controlled by the Open-Drain Control x register,
ODCx, associated with each port. Setting any of the
bits configures the corresponding pin to act as an
open-drain output.
The open-drain feature allows the generation of
outputs other than V
DD by using external pull-up
resistors. The maximum open-drain voltage allowed
on any pin is the same as the maximum VIH
specification for that particular pin.
See the “Pin Diagrams” section for the available 5V
tolerant pins and Table 33-10 for the maximum V
IH
specification for each pin.
11.2 Configuring Analog and Digital
Port Pins
The ANSELx registers control the operation of the
analog port pins. The port pins that are to function as
analog inputs or outputs must have their corresponding
ANSELx and TRISx bits set. In order to use port pins for
I/O functionality with digital modules, such as timers,
UARTs, etc., the corresponding ANSELx bit must be
cleared.
The ANSELx register has a default value of 0xFFFF;
therefore, all pins that share analog functions are
analog (not digital) by default.
Pins with analog functions affected by the ANSELx
registers are listed with a buffer type of analog in the
Pinout I/O Descriptions (see Table 1-1 in Section 1.0
“Device Overview”).
If the TRISx bit is cleared (output) while the ANSELx bit
is set, the digital output level (V
OH or VOL) is converted
by an analog peripheral, such as the ADCx module or
comparator module.
When the PORTx register is read, all pins configured as
analog input channels are read as cleared (a low level).
Pins configured as digital inputs do not convert an
analog input. Analog levels on any pin defined as a
digital input (including the ANx pins) can cause the
input buffer to consume current that exceeds the
device specifications.
11.2.1 I/O PORT WRITE/READ TIMING
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically this instruction
would be a NOP, as shown in Example 11-1.
11.3 Input Change Notification (ICN)
The Input Change Notification function of the I/O ports
allows devices to generate interrupt requests to the
processor in response to a Change-of-State (COS) on
selected input pins. This feature can detect input
Change-of-States (COS), even in Sleep mode when the
clocks are disabled. Every I/O port pin can be selected
(enabled) for generating an interrupt request on a
Change-of-State.
Three control registers are associated with the ICN
functionality of each I/O port. The CNENx registers
contain the ICN interrupt enable control bits for each of
the input pins. Setting any of these bits enables an ICN
interrupt for the corresponding pins.
Each I/O pin also has a weak pull-up and a weak pull-
down connected to it. The pull-ups and pull-downs act
as a current source or sink source connected to the
pin, and eliminate the need for external resistors when
pushbutton or keypad devices are connected. The
pull-ups and pull-downs are enabled separately using
the CNPUx and the CNPDx registers, which contain
the control bits for each of the pins. Setting any of
the control bits enables the weak pull-ups and/or
pull-downs for the corresponding pins.
EXAMPLE 11-1: PORTB WRITE/READ
EXAMPLE
Note: Pull-ups and pull-downs on Input Change
Notification pins should always be dis-
abled when the port pin is configured as a
digital output.
MOV 0xFF00, W0 ; Configure PORTB<15:8>
; as inputs
MOV W0, TRISB ; and PORTB<7:0>
; as outputs
NOP ; Delay 1 cycle
BTSS PORTB, #13 ; Next Instruction