Datasheet

 2013-2014 Microchip Technology Inc. DS70000689D-page 149
dsPIC33EPXXXGM3XX/6XX/7XX
bit 4-0 PLLPRE<4:0>: PLL Phase Detector Input Divider Select bits (also denoted as ‘N1’, PLL prescaler)
11111 = Input divided by 33
•
•
•
00001 = Input divided by 3
00000 = Input divided by 2 (default)
REGISTER 9-2: CLKDIV: CLOCK DIVISOR REGISTER
(2)
(CONTINUED)
Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs.
2: This register resets only on a Power-on Reset (POR).
3: The DOZE<2:0> bits can only be written to when the DOZEN bit is clear. If DOZEN = 1, any writes to
DOZE<2:0> are ignored.
4: The DOZEN bit cannot be set if DOZE<2:0> = 000. If DOZE<2:0> = 000, any attempt by user software to
set the DOZEN bit is ignored.