Datasheet

dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 148  2013-2014 Microchip Technology Inc.
REGISTER 9-2: CLKDIV: CLOCK DIVISOR REGISTER
(2)
R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0
ROI DOZE2
(3)
DOZE1
(3)
DOZE0
(3)
DOZEN
(1,4)
FRCDIV2 FRCDIV1 FRCDIV0
bit 15 bit 8
R/W-0 R/W-1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PLLPOST1 PLLPOST0
— PLLPRE4 PLLPRE3 PLLPRE2 PLLPRE1 PLLPRE0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ROI: Recover on Interrupt bit
1 = Interrupts will clear the DOZEN bit
0 = Interrupts will have no effect on the DOZEN bit
bit 14-12 DOZE<2:0>: Processor Clock Reduction Select bits
(3)
111 = F
CY divided by 128
110 = F
CY divided by 64
101 = F
CY divided by 32
100 = F
CY divided by 16
011 = F
CY divided by 8 (default)
010 = F
CY divided by 4
001 = F
CY divided by 2
000 = F
CY divided by 1
bit 11 DOZEN: Doze Mode Enable bit
(1,4)
1 = DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks
0 = Processor clock and peripheral clock ratio are forced to 1:1
bit 10-8 FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits
111 = FRC divided by 256
110 = FRC divided by 64
101 = FRC divided by 32
100 = FRC divided by 16
011 = FRC divided by 8
010 = FRC divided by 4
001 = FRC divided by 2
000 = FRC divided by 1 (default)
bit 7-6 PLLPOST<1:0>: PLL VCO Output Divider Select bits (also denoted as ‘N2’, PLL postscaler)
11 = Output divided by 8
10 = Reserved
01 = Output divided by 4 (default)
00 = Output divided by 2
bit 5 Unimplemented: Read as ‘0’
Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs.
2: This register resets only on a Power-on Reset (POR).
3: The DOZE<2:0> bits can only be written to when the DOZEN bit is clear. If DOZEN = 1, any writes to
DOZE<2:0> are ignored.
4: The DOZEN bit cannot be set if DOZE<2:0> = 000. If DOZE<2:0> = 000, any attempt by user software to
set the DOZEN bit is ignored.