Datasheet

 2013-2014 Microchip Technology Inc. DS70000689D-page 147

dsPIC33EPXXXGM3XX/6XX/7XX

bit 5 LOCK: PLL Lock Status bit (read-only)

1 = Indicates that PLL is in lock or PLL start-up timer is satisfied

0 = Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled

bit 4 Unimplemented: Read as ‘0’

bit 3 CF: Clock Fail Detect bit (read/clear by application)

(5)

1 = FSCM has detected clock failure

0 = FSCM has not detected clock failure

bit 2 Unimplemented: Read as ‘0’

bit 1 LPOSCEN: Secondary (LP) Oscillator Enable bit

1 = Enables Secondary Oscillator (SOSC)

0 = Disables Secondary Oscillator

bit 0 OSWEN: Oscillator Switch Enable bit

1 = Requests oscillator switch to selection specified by the NOSC<2:0> bits

0 = Oscillator switch is complete

(1,3)

(CONTINUED)

Note 1: Writes to this register require an unlock sequence. Refer to the “dsPIC33/PIC24 Family Reference

Manual”, “Oscillator” (DS70580), available from the Microchip web site for details.

2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.

This applies to clock switches in either direction. In these instances, the application must switch to FRC

mode as a transitional clock source between the two PLL modes.

3: This register resets only on a Power-on Reset (POR).

4: Secondary Oscillator (SOSC) selection is valid on 64-pin and 100-pin devices, and defaults to FRC/N on

44-pin devices.

5: Only ‘0’ should be written to the CF bit in order to clear it. If a ‘1’ is written to CF, it will have the same effect

as a detected clock failure, including an oscillator fail trap.