Datasheet

dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 146  2013-2014 Microchip Technology Inc.
REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER
(1,3)
U-0 R-0 R-0 R-0 U-0 R/W-y R/W-y R/W-y
— COSC2 COSC1 COSC0 —NOSC2
(2)
NOSC1
(2)
NOSC0
(2)
bit 15 bit 8
R/W-0 R/W-0 R-0 U-0 R/W-0 U-0 R/W-0 R/W-0
CLKLOCK IOLOCK LOCK
—CF
(5)
— LPOSCEN OSWEN
bit 7 bit 0
Legend: y = Value set from Configuration bits on POR
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-12 COSC<2:0>: Current Oscillator Selection bits (read-only)
111 = Fast RC Oscillator (FRC) with Divide-by-N
110 = Fast RC Oscillator (FRC) with Divide-by-16
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
(4)
011 = Primary Oscillator (MS, HS, EC) with PLL
010 = Primary Oscillator (MS, HS, EC)
001 = Fast RC Oscillator (FRC) Divided by N and PLL
000 = Fast RC Oscillator (FRC)
bit 11 Unimplemented: Read as ‘0’
bit 10-8 NOSC<2:0>: New Oscillator Selection bits
(2)
111 = Fast RC Oscillator (FRC) with Divide-by-N
110 = Fast RC Oscillator (FRC) with Divide-by-16
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
(4)
011 = Primary Oscillator (MS, HS, EC) with PLL
010 = Primary Oscillator (MS, HS, EC)
001 = Fast RC Oscillator (FRC) Divided by N and PLL
000 = Fast RC Oscillator (FRC)
bit 7 CLKLOCK: Clock Lock Enable bit
1 = If FCKSM0 = 1, then clock and PLL configurations are locked; if FCKSM0 = 0, then clock and PLL
configurations may be modified
0 = Clock and PLL selections are not locked, configurations may be modified
bit 6 IOLOCK: I/O Lock Enable bit
1 = I/O lock is active
0 = I/O lock is not active
Note 1: Writes to this register require an unlock sequence. Refer to the “dsPIC33/PIC24 Family Reference
Manual”, “Oscillator” (DS70580), available from the Microchip web site for details.
2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.
This applies to clock switches in either direction. In these instances, the application must switch to FRC
mode as a transitional clock source between the two PLL modes.
3: This register resets only on a Power-on Reset (POR).
4: Secondary Oscillator (SOSC) selection is valid on 64-pin and 100-pin devices, and defaults to FRC/N on
44-pin devices.
5: Only ‘0’ should be written to the CF bit in order to clear it. If a ‘1’ is written to CF, it will have the same effect
as a detected clock failure, including an oscillator fail trap.