Datasheet

dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 144  2013-2014 Microchip Technology Inc.
9.1 CPU Clocking System
The dsPIC33EPXXXGM3XX/6XX/7XX family of
devices provides seven system clock options:
• Fast RC (FRC) Oscillator
• FRC Oscillator with Phase-Locked Loop (PLL)
• FRC Oscillator with Postscaler
• Primary (XT, HS or EC) Oscillator
• Primary Oscillator with PLL
• Low-Power RC (LPRC) Oscillator
• Secondary (LP) Oscillator
Instruction execution speed or device operating
frequency, FCY, is given by Equation 9-1.
EQUATION 9-1: DEVICE OPERATING
FREQUENCY
Figure 9-2 is a block diagram of the PLL module.
Equation 9-2 provides the relationship between input
frequency (FIN) and output frequency (FOSC).
Equation 9-3 provides the relationship between input
frequency (F
IN) and VCO frequency (FSYS).
FIGURE 9-2: PLL BLOCK DIAGRAM
EQUATION 9-2: F
OSC CALCULATION
EQUATION 9-3: F
VCO CALCULATION
FCY = FOSC/2
÷ N1
÷ M
÷ N2
PFD VCO
PLLPRE<4:0>
PLLDIV<8:0>
PLLPOST<1:0>
0.8 MHz < FPLLI
(1)
< 8.0 MHz
120 MH
Z < FSYS
(1)
< 340 MHZ
FOSC
(1)
 120 MHz @ +125°C
F
IN
FPLLI FSYS FOSC
Note 1: This frequency range must be met at all times.
F
OSC
(1)
 140 MHz @ +85°C
Where:
N1 = PLLPRE<4:0> + 2
N2 = 2 x (PLLPOST<1:0> + 1)
M = PLLDIV<8:0> + 2
(PLLDIV<8:0> + 2)
(PLLPRE<4:0> + 2)  2(PLLPOST<1:0> + 1)
()
FOSC = FIN  = FIN 
M
N1 
 
()
(PLLDIV<8:0> + 2)
(PLLPRE<4:0> + 2)
()
FSYS = FIN  = FIN 
M
N1
()