Datasheet

dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 132  2013-2014 Microchip Technology Inc.
8.1 DMA Controller Registers
Each DMA Controller Channel x (where x = 0 through
3) contains the following registers:
• 16-bit DMA Channel x Control Register (DMAxCON)
• 16-bit DMA Channel x IRQ Select Register (DMAxREQ)
• 32-bit DMA Channel x Start Address Register A
(DMAxSTAL/H)
• 32-bit DMA Channel x Start Address Register B
(DMAxSTBL/H)
• 16-bit DMA Channel x Peripheral Address Register
(DMAxPAD)
• 14-bit DMA Channel x Transfer Count Register
(DMAxCNT)
Additional status registers (DMAPWC, DMARQC,
DMAPPS, DMALCA and DSADRL/H) are common to all
DMA Controller channels. These status registers pro-
vide information on write and request collisions, as well
as on last address and channel access information.
The interrupt flags (DMAxIF) are located in an IFSx
register in the interrupt controller. The corresponding
interrupt enable control bits (DMAxIE) are located in an
IECx register in the interrupt controller and the
corresponding interrupt priority control bits (DMAxIP)
are located in an IPCx register in the interrupt controller.
REGISTER 8-1: DMAXCON: DMA CHANNEL X CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0
CHEN SIZE DIR HALF NULLW — — —
bit 15 bit 8
U-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0
— — AMODE1 AMODE0 — —MODE1MODE0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CHEN: Channel Enable bit
1 = Channel is enabled
0 = Channel is disabled
bit 14 SIZE: Data Transfer Size bit
1 =Byte
0 =Word
bit 13 DIR: Transfer Direction bit (source/destination bus select)
1 = Reads from RAM address, writes to peripheral address
0 = Reads from peripheral address, writes to RAM address
bit 12 HALF: Block Transfer Interrupt Select bit
1 = Initiates interrupt when half of the data has been moved
0 = Initiates interrupt when all of the data has been moved
bit 11 NULLW: Null Data Peripheral Write Mode Select bit
1 = Null data write to peripheral in addition to RAM write (DIR bit must also be clear)
0 = Normal operation
bit 10-6 Unimplemented: Read as ‘0’
bit 5-4 AMODE<1:0>: DMA Channel Addressing Mode Select bits
11 = Reserved
10 = Peripheral Indirect mode
01 = Register Indirect without Post-Increment mode
00 = Register Indirect with Post-Increment mode
bit 3-2 Unimplemented: Read as ‘0’
bit 1-0 MODE<1:0>: DMA Channel Operating Mode Select bits
11 = One-Shot, Ping-Pong modes are enabled (one block transfer from/to each DMA buffer)
10 = Continuous, Ping-Pong modes are enabled
01 = One-Shot, Ping-Pong modes are disabled
00 = Continuous, Ping-Pong modes are disabled