Datasheet

 2013-2014 Microchip Technology Inc. DS70000689D-page 131
dsPIC33EPXXXGM3XX/6XX/7XX
FIGURE 8-2: DMA CONTROLLER BLOCK DIAGRAM
CAN1 – RX Data Ready 00100010 0x0440 (C1RXD) —
CAN1 – TX Data Request 01000110 — 0x0442 (C1TXD)
CAN2 – RX Data Ready 00110111 0X0540(C2RXD) —
CAN2 – TX Data Request 01000111 — 0X0542(C2TXD)
DCI – Codec Transfer Done 00111100 0X0290(RXBUF0) 0X0298(TXBUF0)
ADC1 – ADC1 Convert Done 00001101 0x0300 (ADC1BUF0) —
ADC2 – ADC2 Convert Done 00010101 0X0340(ADC2BUF0) —
PMP – PMP Data Move 00101101 0X0608(PMPDAT1) 0X0608(PMPDAT1)
TABLE 8-1: DMA CHANNEL TO PERIPHERAL ASSOCIATIONS (CONTINUED)
Peripheral to DMA
Association
DMAxREQ Register
IRQSEL<7:0> Bits
DMAxPAD Register
(Values to Read from
Peripheral)
DMAxPAD Register
(Values to Write to
Peripheral)
CPU
Arbiter
Peripheral
Non-DMA
DMA X-Bus
Peripheral Indirect Address
DMA
Control
DMA Controller
DMA
CPU Peripheral X-Bus
IRQ to DMA
and Interrupt
Controller
Modules
IRQ to DMA and
Interrupt Controller
Modules
IRQ to DMA and
Interrupt Controller
Modules
0123
SRAM
Channels
Peripheral 1
DMA
Ready
CPU
DMA
Peripheral 3
DMA
Ready
CPU DMA
Peripheral 2
DMA
Ready
CPU DMA
Note: CPU and DMA address buses are not shown for clarity.