Datasheet

 2013-2014 Microchip Technology Inc. DS70000689D-page 129
dsPIC33EPXXXGM3XX/6XX/7XX
8.0 DIRECT MEMORY ACCESS
(DMA)
The DMA Controller transfers data between Peripheral
Data registers and Data Space SRAM
In addition, DMA can access the entire data memory
space. The data memory bus arbiter is utilized when
either the CPU or DMA attempts to access SRAM,
resulting in potential DMA or CPU stalls.
The DMA Controller supports 4 independent channels.
Each channel can be configured for transfers to or from
selected peripherals. The peripherals supported by the
DMA Controller include:
•CAN
• Analog-to-Digital Converter (ADC)
• Serial Peripheral Interface (SPI)
•UART
• Input Capture
• Output Compare
• DCI
•PMP
•Timers
Refer to Table 8 -1 for a complete list of supported
peripherals.
FIGURE 8-1: PERIPHERAL TO DMA CONTROLLER
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXXGM3XX/6XX/7XX
family of devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to the “dsPIC33/PIC24 Family
Reference Manual”, “Direct Memory
Access (DMA)” (DS70348), which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
DMAPERIPHERAL
Data Memory
SRAM
(see Figure 4-12)
Arbiter