Datasheet

 2013-2014 Microchip Technology Inc. DS70000689D-page 115
dsPIC33EPXXXGM3XX/6XX/7XX
7.0 INTERRUPT CONTROLLER
The dsPIC33EPXXXGM3XX/6XX/7XX interrupt con-
troller reduces the numerous peripheral interrupt
request signals to a single interrupt request signal to
the dsPIC33EPXXXGM3XX/6XX/7XX CPU.
The interrupt controller has the following features:
• Up to eight processor exceptions and software
traps
• Eight user-selectable priority levels
• Interrupt Vector Table (IVT) with a unique vector
for each interrupt or exception source
• Fixed priority within a specified user priority level
• Fixed interrupt entry and return latencies
7.1 Interrupt Vector Table
The dsPIC33EPXXXGM3XX/6XX/7XX Interrupt Vector
Table (IVT), shown in Figure 7-1, resides in program
memory, starting at location, 000004h. The IVT contains
seven non-maskable trap vectors and up to 151 sources
of interrupt. In general, each interrupt source has its own
vector. Each interrupt vector contains a 24-bit-wide
address. The value programmed into each interrupt
vector location is the starting address of the associated
Interrupt Service Routine (ISR).
Interrupt vectors are prioritized in terms of their natural
priority. This priority is linked to their position in the
vector table. Lower addresses generally have a higher
natural priority. For example, the interrupt associated
with Vector 0 takes priority over interrupts at any other
vector address.
7.2 Reset Sequence
A device Reset is not a true exception because the
interrupt controller is not involved in the Reset process.
The dsPIC33EPXXXGM3XX/6XX/7XX devices clear
their registers in response to a Reset, which forces the
PC to zero. The device then begins program execution
at location, 0x000000. A GOTO instruction at the Reset
address can redirect program execution to the
appropriate start-up routine.
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXXGM3XX/6XX/7XX
family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to the “dsPIC33/PIC24 Fam-
ily Reference Manual”, “Interrupts”
(DS70000600), which is available from the
Microchip web site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Note: Any unimplemented or unused vector
locations in the IVT should be pro-
grammed with the address of a default
interrupt handler routine that contains a
RESET instruction.