Datasheet

dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 106  2013-2014 Microchip Technology Inc.
bit 3-0 NVMOP<3:0>: NVM Operation Select bits
(1,3,4)
1111 = Reserved
1110 = Reserved
1101 = Bulk erase primary program Flash memory
1100 = Reserved
1011 = Reserved
1010 = Reserved
0011 = Memory page erase operation
0010 = Memory row program operation with source data from RAM
0001 = Memory double-word program operation
(5)
0000 = Reserved
REGISTER 5-1: NVMCON: NONVOLATILE MEMORY (NVM) CONTROL REGISTER (CONTINUED)
Note 1: These bits can only be reset on POR.
2: If this bit is set, there will be minimal power savings (IIDLE), and upon exiting Idle mode, there is a delay
(T
VREG) before Flash memory becomes operational.
3: All other combinations of NVMOP<3:0> are unimplemented.
4: Execution of the PWRSAV instruction is ignored while any of the NVM operations are in progress.
5: Two adjacent words on a 4-word boundary are programmed during execution of this operation.
6: When URERR is set, the bus mastered row programming operation will terminate with the WRERR bit still set.