Datasheet

 2013-2014 Microchip Technology Inc. DS70000689D-page 105
dsPIC33EPXXXGM3XX/6XX/7XX
REGISTER 5-1: NVMCON: NONVOLATILE MEMORY (NVM) CONTROL REGISTER
R/SO-0
(1)
R/W-0
(1)
R/W-0
(1)
R/W-0 U-0 U-0 R/W-0 R/W-0
WR WREN WRERR NVMSIDL
(2)
— — RPDF URERR
(6)
bit 15 bit 8
U-0 U-0 U-0 U-0 R/W-0
(1)
R/W-0
(1)
R/W-0
(1)
R/W-0
(1)
— — — —NVMOP3
(3,4)
NVMOP2
(3,4)
NVMOP1
(3,4)
NVMOP0
(3,4)
bit 7 bit 0
Legend: SO = Settable Only bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 WR: NVM Write Control bit
(1)
1 = Initiates a Flash memory program or erase operation; the operation is self-timed and the bit is
cleared by hardware once the operation is complete
0 = Program or erase operation is complete and inactive
bit 14 WREN: NVM Write Enable bit
(1)
1 = Enables Flash program/erase operations
0 = Inhibits Flash program/erase operations
bit 13 WRERR: NVM Write Sequence Error Flag bit
(1)
1 = An improper program or erase sequence attempt, or termination has occurred (bit is set automatically
on any set attempt of the WR bit)
0 = The program or erase operation completed normally
bit 12 NVMSIDL: NVM Stop in Idle Control bit
(2)
1 = Flash voltage regulator goes into Standby mode during Idle mode
0 = Flash voltage regulator is active during Idle mode
bit 11-10 Unimplemented: Read as ‘0’
bit 9 RPDF: Bus Mastered Row Programming Data Format Control bit
1 = Row data to be stored in RAM in compressed format
0 = Row data to be stored in RAM in uncompressed format
bit 8 URERR: Bus Mastered Row Programming Data Underrun Error Flag bit
(6)
1 = Indicates that a bus mastered row programming operation has been termination due to a data
underrun error
0 = Indicates no data underrun error is detected
bit 7-4 Unimplemented: Read as ‘0’
Note 1: These bits can only be reset on POR.
2: If this bit is set, there will be minimal power savings (I
IDLE), and upon exiting Idle mode, there is a delay
(T
VREG) before Flash memory becomes operational.
3: All other combinations of NVMOP<3:0> are unimplemented.
4: Execution of the PWRSAV instruction is ignored while any of the NVM operations are in progress.
5: Two adjacent words on a 4-word boundary are programmed during execution of this operation.
6: When URERR is set, the bus mastered row programming operation will terminate with the WRERR bit still set.