dsPIC33EPXXXGM3XX/6XX/7XX 16-Bit Digital Signal Controllers with High-Speed PWM, Op Amps and Advanced Analog Features Operating Conditions Timers/Output Compare/Input Capture • 3.0V to 3.6V, -40°C to +85°C, up to 70 MIPS • 3.0V to 3.
dsPIC33EPXXXGM3XX/6XX/7XX dsPIC33EPXXXGM3XX/6XX/7XX PRODUCT FAMILY The device names, pin counts, memory sizes and peripheral availability of each device are listed in Table 1. Their pinout diagrams appear on the following pages.
dsPIC33EPXXXGM3XX/6XX/7XX Pin Diagrams = Pins are up to 5V tolerant TCK/AN26/CVREF1O/ASCL1/RP40/T4CK/RB8 OA5OUT/AN25/C5IN4-/RP39/INT0/RB7 PGEC2/ASCL2/RP38/RB6 PGED2/ASDA2/RP37/RB5 VDD VSS AN31/CVREF2O/SCL1/RPI53/RC5 AN30/SDA1/RPI52/RC4 AN29/SCK1/RPI51/RC3 AN28/ASDA1/SDI1/RPI25/RA9 OA5IN+/AN24/C5IN3-/C5IN1+/SDO1/RP20/T1CK/RA4 44 43 42 41 40 39 38 37 36 35 34 44-Pin TQFP(1,2) TMS/OA5IN-/AN27/C5IN1-/RP41/RB9 1 33 FLT32/SCL2/RP36/RB4 RP54/PWM6H/RC6 2 32 SDA2/RPI24/RA8 RP55/PWM6L/
dsPIC33EPXXXGM3XX/6XX/7XX Pin Diagrams (Continued) = Pins are up to 5V tolerant OA5IN+/AN24/C5IN3-/C5IN1+/SDO1/RP20/T1CK/RA4 AN28/ASDA1/SDI1/RPI25/RA9 AN29/SCK1/RPI51/RC3 AN30/SDA1/RPI52/RC4 AN31/CVREF2O/SCL1/RPI53/RC5 VSS VDD PGED2/ASDA2/RP37/RB5 PGEC2/ASCL2/RP38/RB6 OA5OUT/AN25/C5IN4-/RP39/INT0/RB7 TCK/AN26/CVREF1O/ASCL1/RP40/T4CK/RB8 44-Pin QFN(1,2,3) 44 43 42 41 40 39 38 37 36 35 34 TMS/OA5IN-/AN27/C5IN1-/RP41/RB9 1 33 FLT32/SCL2/RP36/RB4 RP54/PWM6H/RC6 2 32 SDA2/RPI24/RA8 RP55/PWM6
dsPIC33EPXXXGM3XX/6XX/7XX Pin Diagrams (Continued) = Pins are up to 5V tolerant 50 49 51 52 53 54 56 55 57 58 59 60 62 61 1 48 47 2 3 4 46 45 44 5 6 7 8 43 42 41 dsPIC33EP128GM306/706 dsPIC33EP256GM306/706 dsPIC33EP512GM306/706 9 10 11 12 13 14 15 16 40 39 38 37 36 35 32 31 30 29 28 27 26 25 24 23 22 21 20 19 TCK/AN26/CVREF1O/SOSCO/RP40/T4CK/RB8 SOSCI/RPI61/RC13 OA5OUT/AN25/C5IN4-/RP39/INT0/RB7 AN48/CVREF2O/RPI58/PMCS1/RC10 PGEC2/ASCL2/RP38/PMCS2/RB6 PGED2/ASDA2/RP37/RB5 R
dsPIC33EPXXXGM3XX/6XX/7XX Pin Diagrams (Continued) = Pins are up to 5V tolerant 2: 3: 4: 49 50 RP56/PWM5H/PMWR/RC8 RP55/PWM6L/PMBE/RC7 RP54/PWM6H/RC6 TMS/OA5IN-/AN27/C5IN1-/RP41/RB9 52 51 53 54 55 VDD VCAP RP57/PWM5L/RC9 RP70/RD6 RP69/PMRD/RD5 57 56 RP97/RF1 RPI96/RF0 59 58 RP42/PWM3H/PMD0/RB10 60 48 47 2 3 46 4 5 6 7 45 44 43 42 41 40 39 38 37 dsPIC33EP128GM306/706 dsPIC33EP256GM306/706 dsPIC33EP512GM306/706 8 9 10 11 12 13 14 15 16 36 35 32 31 TCK/AN26/CVREF1O/SOSCO/RP40/T4CK/RB8 SO
dsPIC33EPXXXGM3XX/6XX/7XX Pin Diagrams (Continued) = Pins are up to 5V tolerant 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 TDO/PWM4H/PMD4/RA10 RPI45/PWM2L/CTPLS/PMD3/RB13 RPI44/PWM2H/PMD2/RB12 RP125/RG13 RPI124/RG12 RP126/RG14 RP43/PWM3L/PMD1/RB11 RP42/PWM3H/PMD0/RB10 RF7 RF6 RPI112/RG0 RP113/RG1 RP97/RF1 RPI96/RF0 VDD VCAP RP57/RC9 RP70/RD6 RP69/PMRD/RD5 RP56/PMWR/RC8 RPI77/RD13 RPI76/RD12 RP55/PMBE/RC7 RP54/RC6 TMS/OA5IN-/AN27/C5IN1-/RP41/RB9 100-Pin TQFP(1,2,3) 1 2 3
dsPIC33EPXXXGM3XX/6XX/7XX Pin Diagrams (Continued) 121-Pin TFBGA(1) = Pins are up to 5V tolerant dsPIC33EP128GM310/710 dsPIC33EP256GM310/710 dsPIC33EP512GM310/710 A B C D E F G H J K L Note 1: 1 2 3 4 5 6 7 8 9 10 11 RA10 RB13 RG13 RB10 RG0 RF1 VDD NC RD12 RC6 RB9 NC RG15 RB12 RB11 RF7 RF0 VCAP RD5 RC7 VSS RB8 RB14 VDD RG12 RG14 RF6 NC RC9 RC8 NC RC13 RC10 RD1 RB15 RA7 NC NC NC RD6 RD13 RB7 NC RB6 RD4 RD3 RG6 RD2 NC RG1 NC RA15 RD
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 2: PIN NAMES: dsPIC33EP128/256/512GM310/710 DEVICES(1,2,3) Pin # A1 Full Pin Name TDO/PWM4H/PMD4/RA10 Pin # Full Pin Name E8 AN47/INT4/RA15 A2 RPI45/PWM2L/CTPLS/PMD3/RB13 E9 RPI72/RD8 A3 RP125/RG13 E10 PGED2/ASDA2/RP37/RB5 A4 RP42/PWM3H/PMD0/RB10 E11 AN46/INT3/RA14 A5 RPI112/RG0 F1 MCLR A6 RP97/RF1 F2 AN17/ASDA1/RP120/PMA3/RG8 A7 VDD F3 AN16/RPI121/PMA2/RG9 A8 No Connect F4 AN18/ASCL1/RPI119/PMA4/RG7 A9 RPI76/RD12 F5 VSS A10 RP54/RC6
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 2: PIN NAMES: dsPIC33EP128/256/512GM310/710 DEVICES(1,2,3) (CONTINUED) Pin # Full Pin Name Pin # Full Pin Name E1 PWM6H/T8CK/RD4 J8 No Connect E2 PWM6L/T9CK/RD3 J9 No Connect E3 AN19/RP118/PMA5/RG6 J10 AN41/RP81/RE1 E4 PWM5H/RD2 J11 AN30/SDA1/RPI52/RC4 E5 No Connect K1 PGED3/OA2IN-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 E6 RP113/RG1 K2 PGEC3/CVREF+/OA1OUT/AN3/C1IN4-/C4IN2-/RPI33/ CTED1/RB1 VREF+/AN34/PMA7/RF10 E7 No Connect K3 K4 OA3OUT/AN6/C3IN4-/C4
dsPIC33EPXXXGM3XX/6XX/7XX Table of Contents dsPIC33EPXXXGM3XX/6XX/7XX Product Family ................................................................................................................................ 2 1.0 Device Overview ........................................................................................................................................................................ 15 2.0 Guidelines for Getting Started with 16-Bit Digital Signal Controllers...............................
dsPIC33EPXXXGM3XX/6XX/7XX TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
dsPIC33EPXXXGM3XX/6XX/7XX Referenced Sources This device data sheet is based on the following individual chapters of the “dsPIC33/PIC24 Family Reference Manual”, which are available from the Microchip web site (www.microchip.com). These documents should be considered as the general reference for the operation of a particular module or device feature.
dsPIC33EPXXXGM3XX/6XX/7XX NOTES: DS70000689D-page 14 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX 1.0 This document contains device-specific information for the dsPIC33EPXXXGM3XX/6XX/7XX Digital Signal Controller (DSC) devices. DEVICE OVERVIEW Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGM3XX/6XX/7XX family of devices. It is not intended to be a comprehensive resource. To complement the information in this data sheet, refer to the related section of the “dsPIC33/PIC24 Family Reference Manual”, which is available from the Microchip web site (www.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Name Pin Buffer PPS Type Type Description AN0-AN49 I Analog No Analog Input Channels 0-49. CLKI I No External clock source input. Always associated with OSC1 pin function. CLKO O ST/ CMOS — No Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 1-1: Pin Name PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Buffer PPS Type Type Description U1CTS U1RTS U1RX U1TX I O I O ST — ST — Yes Yes Yes Yes UART1 Clear-to-Send. UART1 Ready-to-Send. UART1 receive. UART1 transmit. U2CTS U2RTS U2RX U2TX I O I O ST — ST — Yes Yes Yes Yes UART2 Clear-to-Send. UART2 Ready-to-Send. UART2 receive. UART2 transmit. U3CTS U3RTS U3RX U3TX I O I O ST — ST — Yes Yes Yes Yes UART3 Clear-to-Send. UART3 Ready-to-Send. UART3 receive.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Buffer PPS Type Type INDX1(1) HOME1(1) QEA1(1) I I I ST ST ST QEB1(1) I ST CNTCMP1(1) O — INDX2(1) HOME2(1) QEA2(1) I I I ST ST ST QEB2(1) I ST Description Yes Quadrature Encoder Index1 pulse input. Yes Quadrature Encoder Home1 pulse input. Yes Quadrature Encoder Phase A input in QEI1 mode. Auxiliary timer external clock input in Timer mode. Yes Quadrature Encoder Phase A input in QEI1 mode.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Buffer PPS Type Type Description PMA0 I/O TTL/ST No PMA1 I/O TTL/ST No PMA2-PMA13 PMBE PMCS1, PMCS2 PMD0-PMD7 O O O I/O — — — TTL/ST No No No No PMRD PMWR O O — — No No Parallel Master Port Address Bit 0 input (Buffered Slave modes) and output (Master modes). Parallel Master Port Address Bit 1 input (Buffered Slave modes) and output (Master modes).
dsPIC33EPXXXGM3XX/6XX/7XX NOTES: DS70000689D-page 20 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX 2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT DIGITAL SIGNAL CONTROLLERS Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGM3XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section of the “dsPIC33/PIC24 Family Reference Manual”, which is available from the Microchip web site (www.microchip.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION 0.1 µF Ceramic 10 µF Tantalum VDD The placement of this capacitor should be close to the VCAP pin. It is recommended that the trace length not exceeds one-quarter inch (6 mm). See Section 30.3 “On-Chip Voltage Regulator” for details. VSS R1 VDD VCAP 2.4 R The MCLR functions: MCLR dsPIC33EP VSS VDD VSS VDD AVSS VDD AVDD VSS 0.1 µF Ceramic 0.1 µF Ceramic 0.
dsPIC33EPXXXGM3XX/6XX/7XX 2.5 ICSP Pins The PGECx and PGEDx pins are used for ICSP and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms.
dsPIC33EPXXXGM3XX/6XX/7XX 2.7 Oscillator Value Conditions on Device Start-up 2.9 • • • • • • • • • • • If the PLL of the target device is enabled and configured for the device start-up oscillator, the maximum oscillator source frequency must be limited to 5 MHz < FIN < 13.6 MHz to comply with device PLL start-up conditions. This means that if the external oscillator frequency is outside this range, the application must start up in the FRC mode first.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 2-5: SINGLE-PHASE SYNCHRONOUS BUCK CONVERTER 12V Input 5V Output I5V PWM ADC Channel PWM FET Driver k7 k1 k2 Op Amp/ Comparator ADC Channel dsPIC33EP FIGURE 2-6: MULTIPHASE SYNCHRONOUS BUCK CONVERTER 3.3V Output FET Driver FET Driver ADC Channel PWM PWM k7 PWM PWM 12V Input k6 PWM PWM FET Driver Op Amp/Comparator k3 Op Amp/Comparator k4 Op Amp/Comparator k5 dsPIC33EP ADC Channel 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 2-7: INTERLEAVED PFC VOUT+ |VAC| k4 VAC k3 k1 k2 VOUT- Op Amp/Comparator FET Driver FET Driver PWM Op Amp/ PWM Comparator Op Amp/ Comparator ADC Channel dsPIC33EP ADC Channel FIGURE 2-8: BEMF VOLTAGE MEASURED USING THE ADC MODULE dsPIC33EP BLDC PWM3H PWM3L PWM2H PWM2L PWM1H PWM1L FLTx 3-Phase Inverter Fault R49 R41 R34 R36 R44 AN2 R52 Demand AN3 AN4 AN5 DS70000689D-page 26 Phase Terminal Voltage Feedback 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX 3.0 CPU Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGM3XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33/PIC24 Family Reference Manual”, “CPU” (DS70359), which is available from the Microchip web site (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 3-1: dsPIC33EPXXXGM3XX/6XX/7XX CPU BLOCK DIAGRAM X Address Bus Y Data Bus X Data Bus Interrupt Controller PSV and Table Data Access 24 Control Block 8 Data Latch Y Data RAM X Data RAM Address Latch Address Latch 16 Y Address Bus PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic Address Latch 16 Data Latch 24 24 16 16 16 16 16 24 16 X RAGU X WAGU 16 Y AGU Program Memory EA MUX 16 Data Latch 24 16 Literal Data IR 24 ROM Latch
dsPIC33EPXXXGM3XX/6XX/7XX 3.5 Programmer’s Model The programmer’s model for the dsPIC33EPXXXGM3XX/ 6XX/7XX devices is shown in Figure 3-2. All registers in the programmer’s model are memory-mapped and can be manipulated directly by instructions. Table 3-1 lists a description of each register. Addressing and Bit-Reversed Addressing, and interrupts. These registers are described in subsequent sections of this document.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 3-2: PROGRAMMER’S MODEL D15 D0 W0 (WREG) W1 W2 W3 W4 W5 DSP Operand Registers W6 W7 Working/Address Registers W8 DSP Address Registers W9 W10 W11 W12 W13 Frame Pointer/W14 Stack Pointer/W15 0 PUSH.s and POP.
dsPIC33EPXXXGM3XX/6XX/7XX 3.
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 3-1: SR: CPU STATUS REGISTER (CONTINUED) bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(1,2) 111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Prior
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 3-2: CORCON: CORE CONTROL REGISTER(3) R/W-0 U-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 VAR — US1 US0 EDT(1) DL2 DL1 DL0 bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R-0 R/W-0 R/W-0 SATA SATB SATDW ACCSAT IPL3(2) SFA RND IF bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 VAR: Variable Exception Processing Latency Contr
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 3-2: CORCON: CORE CONTROL REGISTER(3) (CONTINUED) bit 3 IPL3: CPU Interrupt Priority Level Status bit 3(2) 1 = CPU Interrupt Priority Level is greater than 7 0 = CPU Interrupt Priority Level is 7 or less bit 2 SFA: Stack Frame Active Status bit 1 = Stack frame is active; W14 and W15 address 0x0000 to 0xFFFF, regardless of DSRPAG and DSWPAG values 0 = Stack frame is not active; W14 and W15 address of EDS or Base Data Space bit 1 RND: Rounding Mode Select bit 1 = Bias
dsPIC33EPXXXGM3XX/6XX/7XX 3.7 Arithmetic Logic Unit (ALU) The dsPIC33EPXXXGM3XX/6XX/7XX family ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are two’s complement in nature. Depending on the operation, the ALU can affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register.
dsPIC33EPXXXGM3XX/6XX/7XX NOTES: DS70000689D-page 36 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX 4.0 MEMORY ORGANIZATION Note: 4.1 The program address memory space of the dsPIC33EPXXXGM3XX/6XX/7XX devices is 4M instructions. The space is addressable by a 24-bit value derived either from the 23-bit PC during program execution, or from table operation or Data Space remapping, as described in Section 4.7 “Interfacing Program and Data Memory Spaces”. This data sheet summarizes the features of the dsPIC33EPXXXGM3XX/6XX/ 7XX family of devices.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 4-2: PROGRAM MEMORY MAP FOR dsPIC33EP256GM3XX/6XX/7XX DEVICES(1) GOTO Instruction 0x000000 Reset Address 0x000002 0x000004 0x0001FE 0x000200 User Memory Space Interrupt Vector Table User Program Flash Memory (88K instructions) Flash Configuration Bytes(2) 0x02ABEA 0x02ABEC 0x02ABFE 0x02AC00 Unimplemented (Read ‘0’s) 0x7FFFFE 0x800000 Reserved 0x800FF6 0x800FF8 Configuration Memory Space USERID 0x800FFE 0x801000 Reserved Write Latches Reserved DEVID Reserved 0xF9FF
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 4-3: PROGRAM MEMORY MAP FOR dsPIC33EP512GM3XX/6XX/7XX DEVICES(1) GOTO Instruction 0x000000 Reset Address 0x000002 0x000004 0x0001FE 0x000200 User Memory Space Interrupt Vector Table User Program Flash Memory (175K instructions) Flash Configuration Bytes(2) 0x0557EA 0x0557EC 0x0557FE 0x055800 Unimplemented (Read ‘0’s) 0x7FFFFE 0x800000 Reserved 0x800FF6 0x800FF8 Configuration Memory Space USERID Reserved Write Latches 0xF9FFFE 0xFA0000 0xFA0002 0xFA0004 Reserved
dsPIC33EPXXXGM3XX/6XX/7XX 4.1.1 PROGRAM MEMORY ORGANIZATION 4.1.2 All dsPIC33EPXXXGM3XX/6XX/7XX devices reserve the addresses between 0x000000 and 0x000200 for hard-coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code.
dsPIC33EPXXXGM3XX/6XX/7XX 4.2 Data Address Space The dsPIC33EPXXXGM3XX/6XX/7XX CPU has a separate 16-bit wide data memory space. The Data Space is accessed using separate Address Generation Units (AGUs) for read and write operations. The data memory maps, which are presented by device family and memory size, are shown in Figure 4-5 through Figure 4-7. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the Data Space.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 4-5: DATA MEMORY MAP FOR 128-KBYTE DEVICES MSB Address MSB 4-Kbyte SFR Space LSB 0x0000 0x0001 SFR Space 0x0FFE 0x1000 0x0FFF 0x1001 0x1FFF 0x2001 16-Kbyte SRAM Space LSB Address 16 Bits X Data RAM (X) 0x2FFF 0x3001 8-Kbyte Near Data Space 0x1FFE 0x2000 0x2FFE 0x3000 Y Data RAM (Y) 0x4FFF 0x5001 0x4FFE 0x5000 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory Space (via PSV) 0xFFFF Note: 0xFFFE Memory areas are not shown to scal
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 4-6: DATA MEMORY MAP FOR 256-KBYTE DEVICES MSB Address MSB 4-Kbyte SFR Space LSB 0x0000 0x0001 SFR Space 0x0FFE 0x1000 0x0FFF 0x1001 0x1FFF 0x2001 32-Kbyte SRAM Space LSB Address 16 Bits X Data RAM (X) 0x4FFF 0x5001 0x7FFF 0x8001 0x1FFE 0x2000 0x4FFE 0x5000 Y Data RAM (Y) 0x8FFF 0x9001 0x7FFE 0x8000 0x8FFE 0x9000 Optionally Mapped into Program Memory Space (via PSV) X Data Unimplemented (X) 0xFFFF Note: 8-Kbyte Near Data Space 0xFFFE Memory areas are no
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 4-7: DATA MEMORY MAP FOR 512-KBYTE DEVICES MSB Address MSB 4-Kbyte SFR Space LSB Address 16 Bits LSB 0x0000 0x0001 SFR Space 0x0FFF 0x1001 0x0FFE 0x1000 0x1FFF 0x2001 0x1FFE 0x2000 8-Kbyte Near Data Space X Data RAM (X) 48-Kbyte SRAM Space 0x7FFF 0x8001 0x7FFE 0x8000 0x8FFF 0x9001 0x8FFE 0x9000 Y Data RAM (Y) 0xEFFF 0xD001 0xEFFE 0xD000 Optionally Mapped into Program Memory Space (via PSV) X Data Unimplemented (X) 0xFFFF Note: 0xFFFE Memory areas are no
dsPIC33EPXXXGM3XX/6XX/7XX 4.2.5 X AND Y DATA SPACES The dsPIC33EP core has two Data Spaces: X and Y. These Data Spaces can be considered either separate (for some DSP instructions) or as one unified linear address range (for MCU instructions). The Data Spaces are accessed using two Address Generation Units (AGUs) and separate data paths.
Special Function Register Maps TABLE 4-1: SFR Name Addr. CPU CORE REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets W0 0000 W0 (WREG) xxxx W1 0002 W1 xxxx W2 0004 W2 xxxx W3 0006 W3 xxxx W4 0008 W4 xxxx W5 000A W5 xxxx xxxx W6 000C W6 W7 000E W7 xxxx W8 0010 W8 xxxx 2013-2014 Microchip Technology Inc.
2013-2014 Microchip Technology Inc. TABLE 4-1: SFR Name Addr.
SFR Name Addr. INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXGM6XX/7XX DEVICES Bit 15 INTCON1 08C0 NSTDIS Bit 14 Bit 13 Bit 12 Bit 11 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 2013-2014 Microchip Technology Inc.
2013-2014 Microchip Technology Inc.
SFR Name Addr. INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33EPXXXGM3XX DEVICES Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 INTCON1 08C0 NSTDIS OVAERR OVBERR COVAERR COVBERR Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 2013-2014 Microchip Technology Inc.
2013-2014 Microchip Technology Inc.
SFR Name Addr. TIMERS REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 2013-2014 Microchip Technology Inc.
2013-2014 Microchip Technology Inc. TABLE 4-5: SFR Name INPUT CAPTURE 1 THROUGH INPUT CAPTURE 8 REGISTER MAP Addr.
SFR Name Addr.
2013-2014 Microchip Technology Inc. TABLE 4-6: SFR Name Addr.
PTG REGISTER MAP 2013-2014 Microchip Technology Inc. SFR Name Addr.
2013-2014 Microchip Technology Inc. TABLE 4-8: SFR Name PWM REGISTER MAP Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 SYNCPOL SYNCOEN SYNCEN — — — Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 SEVTPS3 SEVTPS2 Bit 1 Bit 0 All Resets SEVTPS1 SEVTPS0 0000 Addr.
SFR Name Addr.
2013-2014 Microchip Technology Inc. TABLE 4-12: SFR Name Addr.
SFR Name Addr.
2013-2014 Microchip Technology Inc. TABLE 4-15: QEI1 REGISTER MAP SFR Name Addr.
SFR Name QEI2 REGISTER MAP Bit 8 Bit 7 Bit 6 — INTDIV2 HOMPOL IDXPOL Bit 2 Bit 1 Bit 0 All Resets INTDIV1 INTDIV0 CNTPOL GATEN CCM1 CCM0 0000 QEBPOL QEAPOL HOME INDEX QEB QEA 000x Bit 14 Bit 13 Bit 12 Bit 11 QEI2CON 05C0 QEIEN — QEISIDL PIMOD2 PIMOD1 PIMOD0 IMV1 IMV0 QEI2IOC 05C2 QCAPEN FLTREN QFDIV2 QFDIV1 QFDIV0 OUTFNC1 OUTFNC0 SWPAB QEI2STAT 05C4 POS2CNTL 05C6 POSCNT<15:0> 0000 POS2CNTH 05C8 POSCNT<31:16> 0000 POS2HLD 05CA POSHLD<15:0> 0000 VEL
2013-2014 Microchip Technology Inc. TABLE 4-17: SFR Name I2C1 AND I2C2 REGISTER MAP Addr.
UART3 AND UART4 REGISTER MAP SFR Name Addr.
2013-2014 Microchip Technology Inc. TABLE 4-21: SFR Name DCI REGISTER MAP Addr.
SFR Name ADC1 AND ADC2 REGISTER MAP Addr.
2013-2014 Microchip Technology Inc. TABLE 4-22: SFR Name ADC1 AND ADC2 REGISTER MAP (CONTINUED) Addr.
CAN1 REGISTER MAP WHEN WIN (C1CTRL<0>) = 0 OR 1 FOR dsPIC33EPXXXGM60X/7XX DEVICES(1) SFR Name Addr.
2013-2014 Microchip Technology Inc. TABLE 4-25: SFR Name Addr.
SFR Name Addr.
2013-2014 Microchip Technology Inc. TABLE 4-27: SFR Name Addr.
SFR Name Addr.
2013-2014 Microchip Technology Inc. TABLE 4-28: CAN2 REGISTER MAP WHEN WIN (C1CTRL<0>) = 1 FOR dsPIC33EPXXXGM60X/7XX DEVICES(1) (CONTINUED) SFR Name Addr.
PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33EPXXXGM304/604 DEVICES SFR Name Addr.
2013-2014 Microchip Technology Inc. TABLE 4-32: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33EPXXXGM310/710 DEVICES SFR Name Addr.
PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR dsPIC33EPXXXGM60X/7XX DEVICES SFR Name Addr. Bit 15 RPINR0 06A0 — RPINR1 06A2 RPINR3 Bit 14 Bit 13 Bit 12 — — — — 06A6 — — — — RPINR7 06AE — RPINR8 06B0 RPINR9 — 0000 2013-2014 Microchip Technology Inc.
2013-2014 Microchip Technology Inc. TABLE 4-34: PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR dsPIC33EPXXXGM3XX DEVICES SFR Name Addr.
SFR Name NVM REGISTER MAP Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 NVMCON 0728 WR WREN WRERR NVMSIDL — — RPDF URERR — — — — NVMADR 072A NVMADRU 072C — — — — — — — — NVMADRU<23:16> NVMKEY 072E — — — — — — — — NVMKEY<7:0> NVMSRCADRL 0730 NVMSRCADRH 0732 Legend: RCON All Resets NVMOP0 0000 0000 0000 0000 NVMSRCADR<15:1> 0 NVMSRCADRH<23:16> Addr.
2013-2014 Microchip Technology Inc. PARALLEL MASTER/SLAVE PORT REGISTER MAP(2) TABLE 4-38: SFR Name Addr.
SFR Addr.
2013-2014 Microchip Technology Inc. TABLE 4-41: SFR Name OP AMP/COMPARATOR REGISTER MAP Addr.
SFR Name Addr.
2013-2014 Microchip Technology Inc. TABLE 4-45: SFR Name Addr.
SFR Name Addr.
2013-2014 Microchip Technology Inc. TABLE 4-49: SFR Name Addr.
SFR Name PORTC REGISTER MAP FOR dsPIC33EPXXXGM310/710 DEVICES Bit 15 Bit 14 TRISC 0E20 TRISC15 — TRISC<13:0> BFFF PORTC 0E22 RC15 — RC<13:0> xxxx LATC 0E24 LATC15 — LATC<13:0> xxxx ODCC 0E26 ODCC15 — ODCC<13:0> 0000 CNENC 0E28 CNIEC15 — CNIEC<13:0> 0000 CNPUC 0E2A CNPUC15 — CNPUC<13:0> 0000 CNPDC 0E2C CNPDC15 — CNPDC<13:0> ANSELC 0E2E — Legend: Bit 12 — Bit 11 Bit 10 ANSC<12:10> Bit 9 — Bit 8 Bit 7 — Bit 6 — Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2013-2014 Microchip Technology Inc. TABLE 4-55: SFR Name Addr.
SFR Name PORTE REGISTER MAP FOR dsPIC33EPXXXGM306/706 DEVICES Addr.
2013-2014 Microchip Technology Inc. TABLE 4-61: SFR Name Addr.
dsPIC33EPXXXGM3XX/6XX/7XX 4.3.1 PAGED MEMORY SCHEME Construction of the EDS address is shown in Figure 4-8. When DSRPAG<9> = 0 and the base address bit, EA<15> = 1, the DSRPAG<8:0> bits are concatenated onto EA<14:0> to form the 24-bit EDS read address. Similarly, when the base address bit, EA<15> =1, the DSWPAG<8:0> bits are concatenated onto EA<14:0> to form the 24-bit EDS write address.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 4-9: EXTENDED DATA SPACE (EDS) WRITE ADDRESS GENERATION 16-Bit DS EA Byte Select EA<15> = 0 (DSWPAG = Don’t Care) Generate PSV Address No EDS Access 0 EA EA<15> 1 EA DSWPAG<8:0> 9 Bits 15 Bits 24-Bit EDS EA Byte Select Note: DS read access when DSRPAG = 0x000 will force an address error trap. The paged memory scheme provides access to multiple 32-Kbyte windows in the EDS and PSV memory.
PAGED DATA MEMORY SPACE Local Data Space Program Space (Instruction & Data) EDS (DSRPAG<9:0>/DSWPAG<8:0>) DS_Addr<14:0> 0x0000 0x7FFF 0x0000 0x7FFF Page 0 Reserved (Will produce an address error trap) Table Address Space (TBLPAG<7:0>) DS_Addr<15:0> 0x0000 EDS Page 0x001 (DSRPAG = 0x001) (DSWPAG = 0x001) Program Memory (lsw – <15:0>) 0x00_0000 0xFFFF DS_Addr<15:0> 0x0000 0x0000 SFR Registers 0x0FFF 0x1000 0x7FFF 0x0000 Up to 16-Kbyte RAM(1) 0x7FFF 0x4FFF 0x5000 0x7FFF 0x8000 32-Kbyte EDS Window
dsPIC33EPXXXGM3XX/6XX/7XX Allocating different Page registers for read and write access allows the architecture to support data movement between different pages in data memory. This is accomplished by setting the DSRPAG register value to the page from which you want to read and configuring the DSWPAG register to the page to which it needs to be written. Data can also be moved from different PSV to EDS pages by configuring the DSRPAG and DSWPAG registers to address PSV and EDS space, respectively.
dsPIC33EPXXXGM3XX/6XX/7XX 4.3.2 EXTENDED X DATA SPACE The lower portion of the base address space range, between 0x0000 and 0x7FFF, is always accessible regardless of the contents of the Data Space Page registers. It is indirectly addressable through the register indirect instructions. It can be regarded as being located in the default EDS Page 0 (i.e., EDS address range of 0x000000 to 0x007FFF with the base address bit, EA<15> = 0, for this address range).
dsPIC33EPXXXGM3XX/6XX/7XX 4.3.3 DATA MEMORY ARBITRATION AND BUS MASTER PRIORITY that of the CPU maintain the same priority relationship relative to each other. The priority schemes for bus masters with different MSTRPR values are tabulated in Table 4-65. EDS accesses from bus masters in the system are arbitrated.
dsPIC33EPXXXGM3XX/6XX/7XX 4.3.4 SOFTWARE STACK FIGURE 4-13: The W15 register serves as a dedicated Software Stack Pointer (SSP) and is automatically modified by exception processing, subroutine calls and returns; however, W15 can be referenced by any instruction in the same manner as all other W registers. This simplifies reading, writing and manipulating of the Stack Pointer (for example, creating stack frames). To protect against misaligned stack accesses, W15<0> is fixed to ‘0’ by the hardware.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 4-66: FUNDAMENTAL ADDRESSING MODES SUPPORTED Addressing Mode Description File Register Direct The address of the file register is specified explicitly. Register Direct The contents of a register are accessed directly. Register Indirect The contents of Wn form the Effective Address (EA). Register Indirect Post-Modified The contents of Wn form the EA. Wn is post-modified (incremented or decremented) by a constant value.
dsPIC33EPXXXGM3XX/6XX/7XX 4.5 4.5.1 Modulo Addressing Modulo Addressing mode is a method of providing an automated means to support circular data buffers using hardware. The objective is to remove the need for software to perform data address boundary checks when executing tightly looped code, as is typical in many DSP algorithms. Modulo Addressing can operate in either Data or Program Space (since the Data Pointer mechanism is essentially the same for both).
dsPIC33EPXXXGM3XX/6XX/7XX 4.5.3 MODULO ADDRESSING APPLICABILITY Modulo Addressing can be applied to the Effective Address (EA) calculation associated with any W register.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 4-15: BIT-REVERSED ADDRESSING EXAMPLE Sequential Address b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0 Bit Locations Swapped, Left-to-Right, Around Center of Binary Value b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0 Bit-Reversed Address Pivot Point TABLE 4-67: XB = 0x0008 for a 16-Word Bit-Reversed Buffer BIT-REVERSED ADDRESSING SEQUENCE (16-ENTRY) Normal Address Bit-Reversed Address A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal 0 0 0 0 0 0
dsPIC33EPXXXGM3XX/6XX/7XX 4.7 Table instructions allow an application to read or write to small areas of the program memory. This capability makes the method ideal for accessing data tables that need to be updated periodically. It also allows access to all bytes of the program word. The remapping method allows an application to access a large block of data on a read-only basis, which is ideal for look-ups from a large table of static data.
dsPIC33EPXXXGM3XX/6XX/7XX 4.7.1 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the Program Space without going through Data Space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a Program Space word as data. The PC is incremented by two for each successive 24-bit program word.
dsPIC33EPXXXGM3XX/6XX/7XX 5.0 Master Clear (MCLR). This allows customers to manufacture boards with unprogrammed devices and then program the device just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. FLASH PROGRAM MEMORY Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGM3XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source.
dsPIC33EPXXXGM3XX/6XX/7XX 5.2 RTSP Operation RTSP allows the user application to erase a single page of memory, program a row and to program two instruction words at a time. See Table 1 in the “dsPIC33EPXXXGM3XX/6XX/7XX Product Family” section for the page sizes of each device. The Flash program memory array is organized into rows of 64 instructions or 192 bytes.
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 5-1: R/SO-0(1) NVMCON: NONVOLATILE MEMORY (NVM) CONTROL REGISTER R/W-0(1) WR WREN R/W-0(1) WRERR R/W-0 NVMSIDL (2) U-0 U-0 R/W-0 R/W-0 — — RPDF URERR(6) bit 15 bit 8 U-0 U-0 U-0 U-0 — — — — R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1) NVMOP3(3,4) NVMOP2(3,4) NVMOP1(3,4) NVMOP0(3,4) bit 7 bit 0 Legend: SO = Settable Only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cle
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 5-1: NVMCON: NONVOLATILE MEMORY (NVM) CONTROL REGISTER (CONTINUED) NVMOP<3:0>: NVM Operation Select bits(1,3,4) 1111 = Reserved 1110 = Reserved 1101 = Bulk erase primary program Flash memory 1100 = Reserved 1011 = Reserved 1010 = Reserved 0011 = Memory page erase operation 0010 = Memory row program operation with source data from RAM 0001 = Memory double-word program operation(5) 0000 = Reserved bit 3-0 Note 1: 2: 3: 4: 5: 6: These bits can only be reset on POR.
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 5-2: NVMADRU: NONVOLATILE MEMORY UPPER ADDRESS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x NVMADRU<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMADRU<23:16>: Nonvolatile Memory Upper Write Ad
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 5-4: NVMKEY: NONVOLATILE MEMORY KEY REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMKEY<7:0>: NVM Key Register (write-only) bits REGISTER 5-5: x = Bit is unknown NVMSRCADRH: NON
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 5-6: R/W-x NVMSRCADRL: NONVOLATILE DATA MEMORY LOWER ADDRESS REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x NVMSRCADRL<15:8> bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x NVMSRCADRL<7:1> r-0 0 bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-1 NVMSRCADRL<15:1>: Nonvolatile Data Memory Lower Address bits bit 0 R
dsPIC33EPXXXGM3XX/6XX/7XX NOTES: DS70000689D-page 110 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX 6.0 A simplified block diagram of the Reset module is shown in Figure 6-1. RESETS Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGM3XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Reset” (DS70602), which is available from the Microchip web site (www.microchip.com).
dsPIC33EPXXXGM3XX/6XX/7XX RCON: RESET CONTROL REGISTER(1) REGISTER 6-1: R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 TRAPR IOPUWR — — VREGSF — CM VREGS bit 15 bit 8 R/W-0 R/W-0 EXTR SWR R/W-0 (2) SWDTEN R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 WDTO SLEEP IDLE BOR POR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TRAPR: Trap Reset Flag bit 1 = A Trap Conf
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 6-1: RCON: RESET CONTROL REGISTER(1) (CONTINUED) bit 3 SLEEP: Wake-up from Sleep Flag bit 1 = Device was in Sleep mode 0 = Device was not in Sleep mode bit 2 IDLE: Wake-up from Idle Flag bit 1 = Device was in Idle mode 0 = Device was not in Idle mode bit 1 BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred 0 = A Brown-out Reset has not occurred bit 0 POR: Power-on Reset Flag bit 1 = A Power-on Reset has occurred 0 = A Power-on Reset has not occurred
dsPIC33EPXXXGM3XX/6XX/7XX NOTES: DS70000689D-page 114 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX 7.0 INTERRUPT CONTROLLER 7.1 Interrupt Vector Table Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGM3XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Interrupts” (DS70000600), which is available from the Microchip web site (www.microchip.com).
dsPIC33EPXXXGM3XX/6XX/7XX dsPIC33EPXXXGM3XX/6XX/7XX INTERRUPT VECTOR TABLE IVT Decreasing Natural Order Priority FIGURE 7-1: DS70000689D-page 116 Reset – GOTO Instruction 0x000000 Reset – GOTO Address 0x000002 Oscillator Fail Trap Vector 0x000004 Address Error Trap Vector 0x000006 Generic Hard Trap Vector 0x000008 Stack Error Trap Vector 0x00000A Math Error Trap Vector 0x00000C DMA Controller Error Trap Vector 0x00000E Generic Soft Trap Vector 0x000010 Reserved 0x000012 Interrupt Ve
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 7-1: INTERRUPT VECTOR DETAILS Interrupt Source Vector # IRQ # Interrupt Bit Location IVT Address Flag Enable Priority 0x000014 IFS0<0> IEC0<0> IPC0<2:0> Highest Natural Order Priority INT0 – External Interrupt 0 8 0 IC1 – Input Capture 1 9 1 0x000016 IFS0<1> IEC0<1> IPC0<6:4> OC1 – Output Compare 1 10 2 0x000018 IFS0<2> IEC0<2> IPC0<10:8> T1 – Timer1 11 3 0x00001A IFS0<3> IEC0<3> IPC0<14:12> DMA0 – DMA Channel 0 12 4 0x00001C IFS0<4> I
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 7-1: INTERRUPT VECTOR DETAILS (CONTINUED) Vector # Interrupt Source IRQ # Interrupt Bit Location IVT Address Flag Enable Priority IEC2<9> IPC10<6:4> OC5 – Output Compare 5 49 41 0x000066 IFS2<9> OC6 – Output Compare 6 50 42 0x000068 IFS2<10> IEC2<10> IPC10<10:8> OC7 – Output Compare 7 51 43 0x00006A IFS2<11> IEC2<11> IPC10<14:12> OC8 – Output Compare 8 52 44 0x00006C IFS2<12> IEC2<12> IPC11<2:0> PMP – Parallel Master Port(2) 53 45 0x00006E IF
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 7-1: INTERRUPT VECTOR DETAILS (CONTINUED) Interrupt Bit Location Vector # IRQ # SPI3E – SPI3 Error 98 90 0x0000C8 IFS5<10> IEC5<10> IPC22<10:8> SPI3 – SPI3 Transfer Done 99 91 0x0000CA IFS5<11> IEC5<11> IPC22<14:12> 100-101 92-93 0x0000CC-0x0000CE PWM1 – PWM Generator 1 102 94 0x0000D0 IFS5<14> IEC5<14> IPC23<10:8> PWM2 – PWM Generator 2 103 95 0x0000D2 IFS5<15> IEC5<15> IPC23<14:12> Interrupt Source Reserved IVT Address Flag — Enable — Priori
dsPIC33EPXXXGM3XX/6XX/7XX 7.3 Interrupt Control and Status Registers dsPIC33EPXXXGM3XX/6XX/7XX devices implement the following registers for the interrupt controller: • • • • • • • • INTCON1 INTCON2 INTCON3 INTCON4 IFSx IECx IPCx INTTREG 7.3.1 Global interrupt control functions are controlled from INTCON1, INTCON2, INTCON3 and INTCON4. INTCON1 contains the Interrupt Nesting Disable bit (NSTDIS) as well as the control and status flags for the processor trap sources.
dsPIC33EPXXXGM3XX/6XX/7XX SR: CPU STATUS REGISTER(1) REGISTER 7-1: R/W-0 R/W-0 R/W-0 R/W-0 R/C-0 R/C-0 R-0 R/W-0 OA OB SA SB OAB SAB DA DC bit 15 bit 8 R/W-0(3) R/W-0(3) R/W-0(3) R-0 R/W-0 R/W-0 R/W-0 R/W-0 IPL2(2) IPL1(2) IPL0(2) RA N OV Z C bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown IPL<2:0>: CPU Interrupt Priority Level St
dsPIC33EPXXXGM3XX/6XX/7XX CORCON: CORE CONTROL REGISTER(1) REGISTER 7-2: R/W-0 U-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 VAR — US1 US0 EDT DL2 DL1 DL0 bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R-0 R/W-0 R/W-0 SATA SATB SATDW ACCSAT IPL3(2) SFA RND IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 VAR: Variable Exception Processing Latency Control bit 1 = Variable exce
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 NSTDIS: Interrupt
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED) bit 3 ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred bit 2 STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ DS700006
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 GIE DISI SWTRAP — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — INT2EP INT1EP INT0EP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 GIE: Global Interrupt Enable bit 1 = Interrupts and associated IECx bits are enabled 0 = In
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 7-5: INTCON3: INTERRUPT CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — — DAE DOOVR — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-6 Unimplemented: Read as ‘0’ bit 5 DAE: DMA Address Error Soft Trap Status bit 1 = DMA address error soft trap has o
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 7-7: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 — — — — ILR3 ILR2 ILR1 ILR0 bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 VECNUM7 VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 ILR<3:0>: New CPU
dsPIC33EPXXXGM3XX/6XX/7XX NOTES: DS70000689D-page 128 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX 8.0 In addition, DMA can access the entire data memory space. The data memory bus arbiter is utilized when either the CPU or DMA attempts to access SRAM, resulting in potential DMA or CPU stalls. DIRECT MEMORY ACCESS (DMA) Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGM3XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source.
dsPIC33EPXXXGM3XX/6XX/7XX In addition, DMA transfers can be triggered by timers as well as external interrupts. Each DMA channel is unidirectional. Two DMA channels must be allocated to read and write to a peripheral. If more than one channel receives a request to transfer data, a simple fixed priority scheme, based on channel number, dictates which channel completes the transfer and which channel, or channels, are left pending.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 8-1: DMA CHANNEL TO PERIPHERAL ASSOCIATIONS (CONTINUED) Peripheral to DMA Association DMAxREQ Register IRQSEL<7:0> Bits DMAxPAD Register (Values to Read from Peripheral) DMAxPAD Register (Values to Write to Peripheral) 00100010 0x0440 (C1RXD) — CAN1 – RX Data Ready CAN1 – TX Data Request 01000110 — 0x0442 (C1TXD) CAN2 – RX Data Ready 00110111 0X0540(C2RXD) — CAN2 – TX Data Request 01000111 — 0X0542(C2TXD) DCI – Codec Transfer Done 00111100 0X0290(RXBUF0
dsPIC33EPXXXGM3XX/6XX/7XX 8.
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 8-2: DMAXREQ: DMA CHANNEL X IRQ SELECT REGISTER R/S-0 FORCE (1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IRQSEL7 IRQSEL6 IRQSEL5 IRQSEL4 IRQSEL3 IRQSEL2 IRQSEL1 IRQSEL0 bit 7 bit 0 Legend: S = Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 FORCE: Force DMA Transfer bit(
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 8-3: DMAXSTAH: DMA CHANNEL X START ADDRESS REGISTER A (HIGH) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STA<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 STA<23:16>: DMA Primary Start Address bits (sour
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 8-5: DMAXSTBH: DMA CHANNEL X START ADDRESS REGISTER B (HIGH) U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STB<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 STB<23:16>: DMA Secondary Start Address bits (
dsPIC33EPXXXGM3XX/6XX/7XX DMAXPAD: DMA CHANNEL X PERIPHERAL ADDRESS REGISTER(1) REGISTER 8-7: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PAD<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PAD<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 Note 1: x = Bit is unknown PAD<15:0>: DMA Peripheral Address Register bits If the channel is enabled (i.e.
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 8-9: DSADRH: DMA MOST RECENT RAM HIGH ADDRESS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DSADR<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 DSADR<23:16>: Most Recent DMA Address Accessed by DMA bits REGISTER
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 8-11: DMAPWC: DMA PERIPHERAL WRITE COLLISION STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 — — — — PWCOL3 PWCOL2 PWCOL1 PWCOL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-4 Unimplemented: Read as ‘0’ bit 3 PWCOL3: Channel 3 Peripheral Write Collision Flag bit
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 8-12: DMARQC: DMA REQUEST COLLISION STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 — — — — RQCOL3 RQCOL2 RQCOL1 RQCOL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-4 Unimplemented: Read as ‘0’ bit 3 RQCOL3: Channel 3 Transfer Request Collision Flag bit 1 = User
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 8-13: DMALCA: DMA LAST CHANNEL ACTIVE STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 — — — — R-1 R-1 R-1 R-1 LSTCH<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-4 Unimplemented: Read as ‘0’ bit 3-0 LSTCH<3:0>: Last DMA Controller Channel Active Status bits 1111 = No DMA trans
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 8-14: DMAPPS: DMA PING-PONG STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 — — — — PPST3 PPST2 PPST1 PPST0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-4 Unimplemented: Read as ‘0’ bit 3 PPST3: Channel 3 Ping-Pong Mode Status Flag bit 1 = DMA3STB register is se
dsPIC33EPXXXGM3XX/6XX/7XX NOTES: DS70000689D-page 142 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX The dsPIC33EPXXXGM3XX/6XX/7XX oscillator system provides: OSCILLATOR CONFIGURATION Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGM3XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Oscillator” (DS70580), which is available from the Microchip web site (www.microchip.com).
dsPIC33EPXXXGM3XX/6XX/7XX 9.1 The dsPIC33EPXXXGM3XX/6XX/7XX family devices provides seven system clock options: • • • • • • • Instruction execution speed or device operating frequency, FCY, is given by Equation 9-1.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 9-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION Oscillator Mode Fast RC Oscillator with Divide-by-N (FRCDIVN) Oscillator Source See Notes POSCMD<1:0> FNOSC<2:0> Internal xx 111 1, 2 Fast RC Oscillator with Divide-by-16 (FRCDIV16) Internal xx 110 1 Low-Power RC Oscillator (LPRC) Internal xx 101 1 1 Secondary (Timer1) Oscillator (SOSC) Secondary xx 100 Primary Oscillator (HS) with PLL (HSPLL) Primary 10 011 Primary Oscillator (XT) with PLL (XTPLL)
dsPIC33EPXXXGM3XX/6XX/7XX OSCCON: OSCILLATOR CONTROL REGISTER(1,3) REGISTER 9-1: U-0 R-0 — COSC2 R-0 COSC1 R-0 COSC0 U-0 — R/W-y NOSC2 (2) R/W-y NOSC1 (2) R/W-y NOSC0(2) bit 15 bit 8 R/W-0 R/W-0 CLKLOCK IOLOCK R-0 LOCK U-0 — R/W-0 CF (5) U-0 R/W-0 R/W-0 — LPOSCEN OSWEN bit 7 bit 0 Legend: y = Value set from Configuration bits on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is un
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER(1,3) (CONTINUED) bit 5 LOCK: PLL Lock Status bit (read-only) 1 = Indicates that PLL is in lock or PLL start-up timer is satisfied 0 = Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled bit 4 Unimplemented: Read as ‘0’ bit 3 CF: Clock Fail Detect bit (read/clear by application)(5) 1 = FSCM has detected clock failure 0 = FSCM has not detected clock failure bit 2 Unimplemented: Read as ‘0’ bit
dsPIC33EPXXXGM3XX/6XX/7XX CLKDIV: CLOCK DIVISOR REGISTER(2) REGISTER 9-2: R/W-0 R/W-0 (3) ROI DOZE2 R/W-1 DOZE1 R/W-1 (3) (3) DOZE0 R/W-0 (1,4) DOZEN R/W-0 R/W-0 R/W-0 FRCDIV2 FRCDIV1 FRCDIV0 bit 15 bit 8 R/W-0 R/W-1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PLLPOST1 PLLPOST0 — PLLPRE4 PLLPRE3 PLLPRE2 PLLPRE1 PLLPRE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is u
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 9-2: bit 4-0 CLKDIV: CLOCK DIVISOR REGISTER(2) (CONTINUED) PLLPRE<4:0>: PLL Phase Detector Input Divider Select bits (also denoted as ‘N1’, PLL prescaler) 11111 = Input divided by 33 • • • 00001 = Input divided by 3 00000 = Input divided by 2 (default) Note 1: 2: 3: 4: This bit is cleared when the ROI bit is set and an interrupt occurs. This register resets only on a Power-on Reset (POR). The DOZE<2:0> bits can only be written to when the DOZEN bit is clear.
dsPIC33EPXXXGM3XX/6XX/7XX PLLFBD: PLL FEEDBACK DIVISOR REGISTER(1) REGISTER 9-3: U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — PLLDIV<8> bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 PLLDIV<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8-0 PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 9-4: OSCTUN: FRC OSCILLATOR TUNING REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TUN<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits 111111 = Center frequency – 0.
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 9-5: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ROON — ROSSLP ROSEL RODIV3(1) RODIV2(1) RODIV1(1) RODIV0(1) bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ROON: Reference Oscillator Output Enable bit 1 = Reference os
dsPIC33EPXXXGM3XX/6XX/7XX 10.0 POWER-SAVING FEATURES Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGM3XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To _complement the information in this data sheet, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Watchdog Timer and Power-Saving Modes” (DS70615), which is available from the Microchip web site (www.microchip.com).
dsPIC33EPXXXGM3XX/6XX/7XX 10.2.1 SLEEP MODE 10.2.2 IDLE MODE The following occurs in Sleep mode: The following occurs in Idle mode: • The system clock source is shut down. If an on-chip oscillator is used, it is turned off.
dsPIC33EPXXXGM3XX/6XX/7XX 10.3 Doze Mode The preferred strategies for reducing power consumption are changing clock speed and invoking one of the powersaving modes. In some circumstances, this cannot be practical. For example, it may be necessary for an application to maintain uninterrupted synchronous communication, even while it is doing nothing else. Reducing system clock speed can introduce communication errors, while using a power-saving mode can stop communications completely.
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T5MD T4MD T3MD T2MD T1MD QEI1MD PWMMD DCIMD bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 I2C1MD U2MD U1MD SPI2MD SPI1MD C2MD(1) C1MD(1) AD1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 T5MD: Timer5 Modu
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 (CONTINUED) bit 4 SPI2MD: SPI2 Module Disable bit 1 = SPI2 module is disabled 0 = SPI2 module is enabled bit 3 SPI1MD: SPI1 Module Disable bit 1 = SPI1 module is disabled 0 = SPI1 module is enabled bit 2 C2MD: CAN2 Module Disable bit(1) 1 = CAN2 module is disabled 0 = CAN2 module is enabled bit 1 C1MD: CAN1 Module Disable bit(1) 1 = CAN1 module is disabled 0 = CAN1 module is enabled bit 0 AD1MD: ADC1 Modul
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 10-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IC8MD IC7MD IC6MD IC5MD IC4MD IC3MD IC2MD IC1MD bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OC8MD OC7MD OC6MD OC5MD OC4MD OC3MD OC2MD OC1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 IC8MD:IC1MD: Inp
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 10-3: R/W-0 PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3 R/W-0 T9MD T8MD R/W-0 T7MD R/W-0 U-0 — T6MD R/W-0 CMPMD R/W-0 R/W-0 (1) RTCCMD PMPMD bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CRCMD DACMD QEI2MD PWM2MD U3MD I2C3MD I2C2MD ADC2MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 T9MD: Timer9 Module Dis
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 10-3: PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3 bit 3 U3MD: UART3 Module Disable bit 1 = UART3 module is disabled 0 = UART3 module is enabled bit 2 I2C3MD: I2C3 Module Disable bit 1 = I2C3 module is disabled 0 = I2C3 module is enabled bit 1 I2C2MD: I2C2 Module Disable bit 1 = I2C2 module is disabled 0 = I2C2 module is enabled bit 0 ADC2MD: ADC2 Module Disable bit 1 = ADC2 module is disabled 0 = ADC2 module is enabled Note 1: The RTCCMD bit is not availa
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 10-4: PMD4: PERIPHERAL MODULE DISABLE CONTROL REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 U-0 U-0 — — U4MD — REFOMD CTMUMD — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-6 Unimplemented: Read as ‘0’ bit 5 U4MD: UART4 Module Disable bit 1 = UART4 module is disable
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 10-6: U-0 — bit 15 PMD7: PERIPHERAL MODULE DISABLE CONTROL REGISTER 7 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — bit 8 U-0 U-0 — — U-0 — R/W-0 DMA0MD(1) DMA1MD(1) DMA2MD(1) DMA3MD(1) R/W-0 U-0 U-0 U-0 PTGMD — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-5 bit 4 x = Bit is unknown Unimplemented: Read as ‘0’ DMA0MD: DMA0 Module
dsPIC33EPXXXGM3XX/6XX/7XX 11.0 the I/O pin. The logic also prevents “loop through”, in which a port’s digital output can drive the input of a peripheral that shares the same pin. Figure 11-1 illustrates how ports are shared with other peripherals and the associated I/O pin to which they are connected. I/O PORTS Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGM3XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source.
dsPIC33EPXXXGM3XX/6XX/7XX 11.1.1 OPEN-DRAIN CONFIGURATION In addition to the PORTx, LATx and TRISx registers for data control, port pins can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control x register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output. The open-drain feature allows the generation of outputs other than VDD by using external pull-up resistors.
dsPIC33EPXXXGM3XX/6XX/7XX 11.4 Peripheral Pin Select (PPS) A major challenge in general purpose devices is providing the largest possible set of peripheral features while minimizing the conflict of features on I/O pins. The challenge is even greater on low pin count devices. In an application where more than one peripheral needs to be assigned to a single pin, inconvenient work arounds in application code or a complete redesign may be the only option.
dsPIC33EPXXXGM3XX/6XX/7XX 11.4.4 INPUT MAPPING 11.4.4.1 The inputs of the Peripheral Pin Select options are mapped on the basis of the peripheral. That is, a control register associated with a peripheral dictates the pin it will be mapped to. The RPINRx registers are used to configure peripheral input mapping (see Register 11-1 through Register 11-29). Each register contains sets of 7-bit fields, with each set associated with one of the remappable peripherals.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 11-1: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION) Input Name(1) Function Name Register Configuration Bits External Interrupt 1 INT1 RPINR0 INT1R<6:0> External Interrupt 2 INT2 RPINR1 INT2R<6:0> Timer2 External Clock T2CK RPINR3 T2CKR<6:0> Input Capture 1 IC1 RPINR7 IC1R<6:0> Input Capture 2 IC2 RPINR7 IC2R<6:0> Input Capture 3 IC3 RPINR8 IC3R<6:0> Input Capture 4 IC4 RPINR8 IC4R<6:0> Input Capture 5 IC5 RPINR9 IC5R<6:0> Input Captur
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 11-1: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION) (CONTINUED) Input Name(1) Function Name Register Configuration Bits PWM Sync Input 1 SYNCI1 RPINR37 SYNCI1R<6:0> PWM Dead-Time Compensation 1 DTCMP1 RPINR38 DTCMP1R<6:0> PWM Dead-Time Compensation 2 DTCMP2 RPINR39 DTCMP2R<6:0> PWM Dead-Time Compensation 3 DTCMP3 RPINR39 DTCMP3R<6:0> PWM Dead-Time Compensation 4 DTCMP4 RPINR40 DTCMP4R<6:0> PWM Dead-Time Compensation 5 DTCMP5 RPINR40 DTCMP5R<6:
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 11-2: INPUT PIN SELECTION FOR SELECTABLE INPUT SOURCES Peripheral Pin Select Input Register Value Input/ Output Pin Assignment Peripheral Pin Select Input Register Value Input/ Output Pin Assignment 000 0000 I VSS 010 1100 I RPI44 (1) 000 0001 I CMP1 010 1101 I RPI45 000 0010 I CMP2(1) 010 1110 I RPI46 000 0011 I CMP3(1) 010 1111 I RPI47 000 0100 I CMP4(1) 011 0000 I/O RP48 000 0101 — — 011 0001 I/O RP49 000 0110 I PTGO30(1) 011
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 11-2: INPUT PIN SELECTION FOR SELECTABLE INPUT SOURCES (CONTINUED) Peripheral Pin Select Input Register Value Input/ Output Pin Assignment Peripheral Pin Select Input Register Value Input/ Output Pin Assignment 010 1001 I/O RP41 101 0101 — — 010 1010 I/O RP42 101 0110 — — 010 1011 I/O RP43 101 0111 — — 101 1000 — — 110 1100 — — 101 1001 — — 110 1101 — — 101 1010 — — 110 1110 — — 101 1011 — — 110 1111 — — 101 1100 — — 111 00
dsPIC33EPXXXGM3XX/6XX/7XX 11.4.5 OUTPUT MAPPING FIGURE 11-3: In contrast to inputs, the outputs of the Peripheral Pin Select options are mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPORx registers are used to control output mapping. Like the RPINRx registers, each register contains sets of 6-bit fields, with each set associated with one RPn pin (see Register 11-30 through Register 11-42).
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 11-3: OUTPUT SELECTION FOR REMAPPABLE PINS (RPn) Function RPnR<5:0> Output Name Default Port 000000 RPn tied to Default Pin U1TX 000001 RPn tied to UART1 Transmit U2TX 000011 RPn tied to UART2 Transmit SDO2 001000 RPn tied to SPI2 Data Output SCK2 001001 RPn tied to SPI2 Clock Output SS2 001010 RPn tied to SPI2 Slave Select CSDO 001011 RPn tied to DCI Data Output CSCK 001100 RPn tied to DCI Clock Output COFS 001101 RPn tied to DCI Frame Sync C1
dsPIC33EPXXXGM3XX/6XX/7XX 11.5 High-Voltage Detect 3. The dsPIC33EPXXXGM3XX/6XX/7XX devices contain High-Voltage Detection (HVD) which monitors the VCAP voltage. The HVD is used to monitor the VCAP supply voltage to ensure that an external connection does not raise the value above a safe level (~2.4V). If high core voltage is detected, all I/Os are disabled and put in a tri-state condition. The device remains in this I/O tristate condition as long as the high-voltage condition is present. 11.6 1. 2.
dsPIC33EPXXXGM3XX/6XX/7XX 6. The Peripheral Pin Select (PPS) pin mapping rules are as follows: a) Only one “output” function can be active on a given pin at any time, regardless if it is a dedicated or remappable function (one pin, one output). b) It is possible to assign a “remappable output” function to multiple pins and externally short or tie them together for increased current drive.
dsPIC33EPXXXGM3XX/6XX/7XX 11.
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 11-2: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INT2R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-0 INT2R<6:0>: Assign External Interrupt 2 (INT2) to the
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 11-3: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T2CKR<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-0 T2CKR<6:0>: Assign Timer2 External Clock (T2CK) to the
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 11-4: U-0 RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7 R/W-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 IC2R<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IC1R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 IC2R<6:0>: Assign Input Capture 2 (IC2) to the Corresp
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 11-5: U-0 RPINR8: PERIPHERAL PIN SELECT INPUT REGISTER 8 R/W-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 IC4R<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IC3R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 IC4R<6:0>: Assign Input Capture 4 (IC4) to the Corresp
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 11-6: U-0 RPINR9: PERIPHERAL PIN SELECT INPUT REGISTER 9 R/W-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 IC6R<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IC5R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 IC6R<6:0>: Assign Input Capture 6 (IC6) to the Corresp
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 11-7: U-0 RPINR10: PERIPHERAL PIN SELECT INPUT REGISTER 10 R/W-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 IC8R<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IC7R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 IC8R<6:0>: Assign Input Capture 8 (IC8) to the Corre
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 11-8: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OCFAR<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-0 OCFAR<6:0>: Assign Output Compare Fault A (OCFA) to
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 11-9: U-0 RPINR12: PERIPHERAL PIN SELECT INPUT REGISTER 12 R/W-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 FLT2R<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLT1R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 FLT2R<6:0>: Assign PWM Fault 2 (FLT2) to the Corre
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 11-10: RPINR14: PERIPHERAL PIN SELECT INPUT REGISTER 14 U-0 R/W-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 QEB1R<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 QEA1R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 QEB1R<6:0>: Assign QEI1 Phase B (QEB1) to the Cor
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 11-11: RPINR15: PERIPHERAL PIN SELECT INPUT REGISTER 15 U-0 R/W-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 HOME1R<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INDX1R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 HOME1R<6:0>: Assign QEI1 HOME (HOME1) to the Co
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 11-12: RPINR16: PERIPHERAL PIN SELECT INPUT REGISTER 16 U-0 R/W-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 QEB2R<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 QEA2R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 QEB2R<6:0>: Assign QEI2 Phase B (QEB2) to the Cor
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 11-13: RPINR17: PERIPHERAL PIN SELECT INPUT REGISTER 17 U-0 R/W-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 HOME2R<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INDX2R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 HOME2R<6:0>: Assign QEI2 HOME (HOME2) to the Co
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 11-14: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 U1RXR<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-0 U1RXR<6:0>: Assign UART1 Receive (U1RX) to the Corres
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 11-16: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22 U-0 R/W-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 SCK2R<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SDI2R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 SCK2R<6:0>: Assign SPI2 Clock Input (SCK2) to the
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 11-17: RPINR23: PERIPHERAL PIN SELECT INPUT REGISTER 23 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SS2R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-0 SS2R<6:0>: Assign SPI2 Slave Select (SS2) to the Corre
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 11-18: RPINR24: PERIPHERAL PIN SELECT INPUT REGISTER 24 U-0 R/W-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 CSCK2R<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSDIR<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 CSCK2R<6:0>: Assign DCI Clock Input (CSCK) to th
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 11-19: RPINR25: PERIPHERAL PIN SELECT INPUT REGISTER 25 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 COFSR<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-0 COFSR<6:0>: Assign DCI Frame Sync Input (COFS) to the
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 11-20: RPINR26: PERIPHERAL PIN SELECT INPUT REGISTER 26(1) U-0 R/W-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 C2RXR<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C1RXR<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 C2RXR<6:0>: Assign CAN2 RX Input (C2RX) to the
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 11-21: RPINR27: PERIPHERAL PIN SELECT INPUT REGISTER 27 U-0 R/W-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 U3CTSR<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U3RXR<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 U3CTSR<6:0>: Assign UART3 Clear-to-Send (U3CTS)
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 11-22: RPINR28: PERIPHERAL PIN SELECT INPUT REGISTER 28 U-0 R/W-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 U4CTSR<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U4RXR<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 U4CTSR<6:0>: Assign UART4 Clear-to-Send (U4CTS)
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 11-23: RPINR29: PERIPHERAL PIN SELECT INPUT REGISTER 29 U-0 R/W-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 SCK3R<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SDI3R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 SCK3R<6:0>: Assign SPI3 Clock Input (SCK3) to the
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 11-24: RPINR30: PERIPHERAL PIN SELECT INPUT REGISTER 30 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SS3R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-0 SS3R<6:0>: Assign SPI3 Slave Select Input (SS3) to the
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 11-25: RPINR37: PERIPHERAL PIN SELECT INPUT REGISTER 37 U-0 R/W-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 SYNCI1R<6:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 SYNCI1R<6:0>: Assign PWM Synchronization Input 1 to
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 11-26: RPINR38: PERIPHERAL PIN SELECT INPUT REGISTER 38 U-0 R/W-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 DTCMP1R<6:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 DTCMP1R<6:0>: Assign PWM Dead-Time Compensation Inpu
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 11-27: RPINR39: PERIPHERAL PIN SELECT INPUT REGISTER 39 U-0 R/W-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 DTCMP3R<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DTCMP2R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 DTCMP3R<6:0>: Assign PWM Dead-Time Compensati
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 11-28: RPINR40: PERIPHERAL PIN SELECT INPUT REGISTER 40 U-0 R/W-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 DTCMP5R<6:0> bit 15 bit 8 U-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DTCMP4R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 DTCMP5R<6:0>: Assign PWM Dead-Time Compensati
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 11-29: RPINR41: PERIPHERAL PIN SELECT INPUT REGISTER 41 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DTCMP6R<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-0 DTCMP6R<6:0>: Assign PWM Dead-Time Compensation Inp
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 11-30: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP35R<5:0> bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP20R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP35R<5:0>: Peripheral Output Function is Assi
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 11-32: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP39R<5:0> bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP38R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP39R<5:0>: Peripheral Output Function is Assi
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 11-34: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP43R<5:0> bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP42R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP43R<5:0>: Peripheral Output Function is Assi
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 11-36: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP55R<5:0> bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP54R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP55R<5:0>: Peripheral Output Function is Assi
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 11-38: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8(1) U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP70R<5:0> bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP69R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP70R<5:0>: Peripheral Output Function is A
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 11-40: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10(1) U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP118R<5:0> bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP113R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP118R<5:0>: Peripheral Output Function
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 11-42: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12(1) U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP127R<5:0> bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP126R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP127R<5:0>: Peripheral Output Function
dsPIC33EPXXXGM3XX/6XX/7XX NOTES: DS70000689D-page 210 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX 12.0 The Timer1 module can operate in one of the following modes: TIMER1 Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGM3XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Timers” (DS70362), which is available from the Microchip web site (www.microchip.com).
dsPIC33EPXXXGM3XX/6XX/7XX 12.
dsPIC33EPXXXGM3XX/6XX/7XX 13.0 TIMER2/3, TIMER4/5, TIMER6/7 AND TIMER8/9 Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGM3XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Timers” (DS70362), which is available from the Microchip web site (www.microchip.com).
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 13-1: TYPE B TIMER BLOCK DIAGRAM (x = 2, 4, 6 AND 8) Gate Sync Falling Edge Detect 1 Set TxIF Flag 0 FP (1) Prescaler (/n) 10 TxCLK TGATE 00 TCKPS<1:0> Reset TMRx Data Latch CLK TxCK Prescaler (/n) Sync x1 Comparator TGATE TCKPS<1:0> TCS Note 1: Equal PRx FP is the peripheral clock.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 13-3: TYPE B/TYPE C TIMER PAIR BLOCK DIAGRAM (32-BIT TIMER) Falling Edge Detect Gate Sync 1 Set TyIF Flag(4) PRx(3) PRy(4) 0 TGATE Equal Comparator FP(1) TxCK(3) Prescaler (/n) 10 TCKPS<1:0> 00 Prescaler (/n) lsw Sync Data msw TMRx(3) ADCx(2) TMRy(4) Latch CLK Reset x1 TMRyHLD(4) TCKPS<1:0> TGATE TCS Data Bus<15:0> Note 1: 2: 3: 4: FP is the peripheral clock. The ADCX trigger is available only on the TMR3:TMR2 andTMR5:TMR4 32-bit timer pairs.
dsPIC33EPXXXGM3XX/6XX/7XX 13.
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 13-2: TyCON (T3CON, T5CON, T7CON AND T9CON) CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON(1) — TSIDL(2) — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 — TGATE(1) TCKPS1(1) TCKPS0(1) — — TCS(1,3) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timery On bit(1) 1 = Starts 16-bit Timery 0 = Stops
dsPIC33EPXXXGM3XX/6XX/7XX NOTES: DS70000689D-page 218 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX 14.0 INPUT CAPTURE Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGM3XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Input Capture” (DS70000352), which is available from the Microchip web site (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices.
dsPIC33EPXXXGM3XX/6XX/7XX 14.
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 14-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — IC32(1) bit 15 bit 8 R/W-0 R/W/HS-0 U-0 ICTRIG(2) TRIGSTAT(3) — R/W-0 R/W-1 R/W-1 R/W-0 R/W-1 SYNCSEL4(4) SYNCSEL3(4) SYNCSEL2(4) SYNCSEL1(4) SYNCSEL0(4) bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 14-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2 (CONTINUED) SYNCSEL<4:0>: Input Source Select for Synchronization and Trigger Operation bits(4) 11111 = Capture timer is unsynchronized 11110 = Capture timer is unsynchronized 11101 = Capture timer is unsynchronized 11100 = CTMU trigger is the source for the capture timer synchronization 11011 = ADC1 interrupt is the source for the capture timer synchronization(5) 11010 = Analog Comparator 3 is the source for the capture
dsPIC33EPXXXGM3XX/6XX/7XX 15.0 The output compare module can select one of eight available clock sources for its time base. The module compares the value of the timer with the value of one or two Compare registers depending on the operating mode selected. The state of the output pin changes when the timer value matches the Compare register value.
dsPIC33EPXXXGM3XX/6XX/7XX 15.
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 15-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 (CONTINUED) bit 3 TRIGMODE: Trigger Status Mode Select bit 1 = TRIGSTAT (OCxCON2<6>) is cleared when OCxRS = OCxTMR or in software 0 = TRIGSTAT is cleared only by software bit 2-0 OCM<2:0>: Output Compare x Mode Select bits 111 = Center-Aligned PWM mode: Output sets high when OCxTMR = OCxR and sets low when OCxTMR = OCxRS(1) 110 = Edge-Aligned PWM mode: Output sets high when OCxTMR = 0 and sets low when OCxTMR = OCxR(
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 15-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 FLTMD FLTOUT FLTTRIEN OCINV — — — OC32 bit 15 bit 8 R/W-0 R/W-0, HS R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cle
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 15-2: bit 4-0 OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 (CONTINUED) SYNCSEL<4:0>: Trigger/Synchronization Source Selection bits 11111 = OCxRS compare event is used for synchronization 11110 = INT2 is the source for compare timer synchronization 11101 = INT1 is the source for compare timer synchronization 11100 = CTMU trigger is the source for compare timer synchronization 11011 = ADC1 interrupt is the source for compare timer synchronization 11010 = Analog Comparator
dsPIC33EPXXXGM3XX/6XX/7XX NOTES: DS70000689D-page 228 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX 16.0 HIGH-SPEED PWM MODULE Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGM3XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33/PIC24 Family Reference Manual”, “High-Speed PWM” (DS70645), which is available from the Microchip web site (www.microchip.com).
dsPIC33EPXXXGM3XX/6XX/7XX 16.1.2 WRITE-PROTECTED REGISTERS On dsPIC33EPXXXGM3XX/6XX/7XX devices, write protection is implemented for the IOCONx and FCLCONx registers. The write protection feature prevents any inadvertent writes to these registers. This protection feature can be controlled by the PWMLOCK Configuration bit (FOSCSEL<6>). The default state of the write protection feature is enabled (PWMLOCK = 1). The write protection feature can be disabled by configuring: PWMLOCK = 0.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 16-1: HIGH-SPEED PWMx MODULE ARCHITECTURAL OVERVIEW SYNCI1 Data Bus FOSC Master Time Base Synchronization Signal PWM1 Interrupt SYNCO1 PWM1H PWM Generator 1 PWM1L Fault, Current-Limit and Dead-Time Compensation Synchronization Signal CPU PWM2-PWM5 Interrupt PWM Generator 2 through Generator 5 PWM2H-PWM5H PWM2L-PWM5L Fault, Current-Limit and Dead-Time Compensation Synchronization Signal PWM6 Interrupt PWM6H PWM Generator 6 Primary Trigger ADCx Module Primary Sp
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 16-2: HIGH-SPEED PWMx MODULE REGISTER INTERCONNECTION DIAGRAM FOSC PTCON, PTCON2 SYNCI1 Module Control and Timing PTPER SEVTCMP Comparator Comparator SYNCO1 Special Event Compare Trigger Special Event Postscaler Special Event Trigger Master Time Base Counter Clock Prescaler PMTMR PTPER Comparator Primary Master Time Base SYNCO2 Special Event Compare Trigger SEVTCMP Special Event Postscaler Comparator Special Event Trigger Master Time Base Counter Cloc
dsPIC33EPXXXGM3XX/6XX/7XX 16.
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 16-1: PTCON: PWMx TIME BASE CONTROL REGISTER (CONTINUED) bit 6-4 SYNCSRC<2:0>: Synchronous Source Selection bits(1) 111 = Reserved • • • 100 = Reserved 011 = PTGO17(2) 010 = PTGO16(2) 001 = Reserved 000 = SYNCI1 bit 3-0 SEVTPS<3:0>: PWMx Special Event Trigger Output Postscaler Select bits(1) 1111 = 1:16 Postscaler generates Special Event Trigger on every sixteenth compare match event • • • 0001 = 1:2 Postscaler generates Special Event Trigger on every second compare m
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 16-2: PTCON2: PWMx PRIMARY MASTER CLOCK DIVIDER SELECT REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 R/W-0 PCLKDIV<2:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 PCLKDIV<2:0>: PWMx Input Clock Prescaler (Divider) S
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 16-3: R/W-1 PTPER: PWMx PRIMARY MASTER TIME BASE PERIOD REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 PTPER<15:8> bit 15 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 PTPER<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown PTPER<15:0>: Primary Master Time Base (PMTMR) Period Value bits REGISTER 16-4: R/W-0
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 16-5: STCON: PWMx SECONDARY TIME BASE CONTROL REGISTER U-0 U-0 U-0 HS/HC-0 R/W-0 R/W-0 — — — SESTAT SEIEN EIPU(1) R/W-0 R/W-0 SYNCPOL(1) SYNCOEN(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SYNCEN(1) SYNCSRC2(1) SYNCSRC1(1) SYNCSRC0(1) SEVTPS3(1) SEVTPS2(1) SEVTPS1(1) R/W-0 SEVTPS0(1) bit 7 bit 0 Legend: HC = Hardware Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 16-5: STCON: PWMx SECONDARY TIME BASE CONTROL REGISTER (CONTINUED) SEVTPS<3:0>: PWMx Special Event Trigger Output Postscaler Select bits(1) 1111 = 1:16 Postscaler generates the Special Event Trigger on every sixteenth compare match event • • • 0001 = 1:2 Postscaler generates the Special Event Trigger on every second compare match event 0000 = 1:1 Postscaler generates the Special Event Trigger on every compare match event bit 3-0 Note 1: 2: These bits should be change
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 16-6: STCON2: PWMx SECONDARY MASTER CLOCK DIVIDER SELECT REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 R/W-0 PCLKDIV<2:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 PCLKDIV<2:0>: PWMx Input Clock Prescaler (Divider)
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 16-7: R/W-1 STPER: PWMx SECONDARY MASTER TIME BASE PERIOD REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 STPER<15:8> bit 15 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 STPER<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown STPER<15:0>: PWMx Secondary Master Time Base (PMTMR) Period Value bits REGISTER 16
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 16-9: CHOP: PWMx CHOP CLOCK GENERATOR REGISTER R/W-0 U-0 U-0 U-0 U-0 U-0 CHPCLKEN — — — — — R/W-0 R/W-0 CHOPCLK9 CHOPCLK8 bit 15 bit 8 R/W-0 CHOPCLK7 R/W-0 R/W-0 R/W-0 R/W-0 CHOPCLK6 CHOPCLK5 CHOPCLK4 CHOPCLK3 R/W-0 CHOPCLK2 R/W-0 R/W-0 CHOPCLK1 CHOPCLK0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CHPCLKEN: En
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 16-11: PWMCONx: PWMx CONTROL REGISTER HS/HC-0 FLTSTAT (1) HS/HC-0 CLSTAT(1) HS/HC-0 TRGSTAT R/W-0 FLTIEN R/W-0 CLIEN R/W-0 R/W-0 R/W-0 TRGIEN ITB(2) MDCS(2) bit 15 bit 8 R/W-0 R/W-0 DTC1 DTC0 R/W-0 DTCP (3) U-0 — R/W-0 R/W-0 R/W-0 R/W-0 MTBS CAM(2,4) XPRES(5) IUE(2) bit 7 bit 0 Legend: HC = Hardware Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 16-11: PWMCONx: PWMx CONTROL REGISTER (CONTINUED) bit 7-6 DTC<1:0>: Dead-Time Control bits 11 = Dead-Time Compensation mode 10 = Dead-time function is disabled 01 = Negative dead time is actively applied for Complementary Output mode 00 = Positive dead time is actively applied for all Output modes bit 5 DTCP: Dead-Time Compensation Polarity bit(3) When Set to ‘1’: If DTCMPx = 0, PWMxL is shortened and PWMxH is lengthened.
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 16-12: PDCx: PWMx GENERATOR DUTY CYCLE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDCx<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDCx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown PDCx<15:0>: PWMx Generator # Duty Cycle Value bits REGISTER 16-13: SDCx: PWMx SECONDARY DUTY CYCL
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 16-14: PHASEx: PWMx PRIMARY PHASE-SHIFT REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHASEx<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHASEx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown PHASEx<15:0>: Phase-Shift Value or Independent Time Base Period for the PWMx Generator bits
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 16-16: DTRx: PWMx DEAD-TIME REGISTER U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DTRx<13:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DTRx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-0 DTRx<13:0>: Unsigned 14-Bit Dead-Time Value for PWMx Dead-Time Unit
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 16-18: TRGCONx: PWMx TRIGGER CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 TRGDIV3 TRGDIV2 TRGDIV1 TRGDIV0 — — — — bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 (1) TRGSTRT5 R/W-0 (1) TRGSTRT5 R/W-0 (1) TRGSTRT5 R/W-0 (1) TRGSTRT5 R/W-0 (1) TRGSTRT5 TRGSTRT5(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 16-19: IOCONx: PWMx I/O CONTROL REGISTER(2) R/W-1 R/W-1 PENH PENL R/W-0 POLH R/W-0 R/W-0 POLL PMOD1 (1) R/W-0 PMOD0 (1) R/W-0 R/W-0 OVRENH OVRENL bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OVRDAT1 OVRDAT0 FLTDAT1 FLTDAT0 CLDAT1 CLDAT0 SWAP OSYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 16-19: IOCONx: PWMx I/O CONTROL REGISTER(2) (CONTINUED) bit 1 SWAP: SWAP PWMxH and PWMxL Pins bit 1 = PWMxH output signal is connected to the PWMxL pins; PWMxL output signal is connected to the PWMxH pins 0 = PWMxH and PWMxL pins are mapped to their respective pins bit 0 OSYNC: Output Override Synchronization bit 1 = Output overrides via the OVRDAT<1:0> bits are synchronized to the PWM time base 0 = Output overrides via the OVDDAT<1:0> bits occur on the next CPU clock b
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 16-21: FCLCONx: PWMx FAULT CURRENT-LIMIT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IFLTMOD CLSRC4 CLSRC3 CLSRC2 CLSRC1 CLSRC0 CLPOL(1) CLMOD bit 15 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 FLTSRC4 FLTSRC3 FLTSRC2 FLTSRC1 FLTSRC0 FLTPOL(1) FLTMOD1 FLTMOD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 16-21: FCLCONx: PWMx FAULT CURRENT-LIMIT CONTROL REGISTER (CONTINUED) bit 7-3 FLTSRC<4:0>: Fault Control Signal Source Select for PWMx Generator # bits 11111 = Fault 32 (default) 11110 = Reserved • • • 01100 = Op Amp/Comparator 5 01011 = Comparator 4 01010 = Op Amp/Comparator 3 01001 = Op Amp/Comparator 2 01000 = Op Amp/Comparator 1 00111 = Fault 8 00110 = Fault 7 00101 = Fault 6 00100 = Fault 5 00011 = Fault 4 00010 = Fault 3 00001 = Fault 2 00000 = Fault 1 bit 2 FLTPO
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 16-22: LEBCONx: LEADING-EDGE BLANKING CONTROL REGISTER x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 PHR PHF PLR PLF FLTLEBEN CLLEBEN — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — BCH(1) BCL(1) BPHH BPHL BPLH BPLL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PHR: PWMxH Rising Edge Trigge
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 16-23: LEBDLYx: LEADING-EDGE BLANKING DELAY REGISTER x U-0 U-0 U-0 U-0 — — — — R/W-0 R/W-0 R/W-0 R/W-0 LEB<11:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEB<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11-0 LEB<11:0>: Leading-Edge Blanking Delay for Curren
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 16-24: AUXCONx: PWMx AUXILIARY CONTROL REGISTER U-0 U-0 U-0 U-0 — — — — R/W-0 R/W-0 R/W-0 R/W-0 BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0 bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 R/W-0 CHOPSEL3 CHOPSEL2 CHOPSEL1 R/W-0 R/W-0 R/W-0 CHOPSEL0 CHOPHEN CHOPLEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented:
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 16-25: PWMCAPx: PWMx PRIMARY TIME BASE CAPTURE REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 (1,2) PWMCAPx<15:8> bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 PWMCAPx<7:0> R-0 R-0 R-0 (1,2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 Note 1: 2: x = Bit is unknown PWMCAPx<15:0>: PWMx Captured Time Base Value bits(1,2) The value in this register represe
dsPIC33EPXXXGM3XX/6XX/7XX NOTES: DS70000689D-page 256 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX 17.0 QUADRATURE ENCODER INTERFACE (QEI) MODULE Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGM3XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Quadrature Encoder Interface (QEI)” (DS70601) which is available from the Microchip web site (www.microchip.com).
QEIx BLOCK DIAGRAM FLTREN GATEN FHOMEx HOMEx DIR_GATE FP QFDIV INDXx 1 COUNT COUNT_EN EXTCNT 0 DIVCLK FINDXx CCM Digital Filter Quadrature Decoder Logic QEBx DIR DIR_GATE COUNT CNT_DIR 1’b0 DIR CNTPOL EXTCNT QEAx DIR_GATE PCHGE PCLLE CNTCMPx PCLLE PCHEQ PCLEQ PCHGE 32-Bit Less Than or Equal Comparator OUTFNC 32-Bit Greater Than or Equal Comparator PCLLE FP INTDIV DIVCLK 32-Bit Less Than or Equal Compare Register (QEI1LEC) COUNT_EN 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX 17.
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 17-1: QEIxCON: QEIx CONTROL REGISTER (CONTINUED) bit 6-4 INTDIV<2:0>: Timer Input Clock Prescale Select bits (interval timer, main timer (position counter), velocity counter and index counter internal clock divider select)(3) 111 = 1:128 prescale value 110 = 1:64 prescale value 101 = 1:32 prescale value 100 = 1:16 prescale value 011 = 1:8 prescale value 010 = 1:4 prescale value 001 = 1:2 prescale value 000 = 1:1 prescale value bit 3 CNTPOL: Position and Index Counter/
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 17-2: QEIxIOC: QEIx I/O CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 QCAPEN FLTREN QFDIV2 QFDIV1 QFDIV0 OUTFNC1 OUTFNC0 SWPAB bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R-x R-x R-x R-x HOMPOL IDXPOL QEBPOL QEAPOL HOME INDEX QEB QEA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 QCAPEN: QEIx P
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 17-2: QEIxIOC: QEIx I/O CONTROL REGISTER (CONTINUED) bit 2 INDEX: Status of INDXx Input Pin After Polarity Control bit 1 = Pin is at logic ‘1’ 0 = Pin is at logic ‘0’ bit 1 QEB: Status of QEBx Input Pin After Polarity Control and SWPAB Pin Swapping bit 1 = Pin is at logic ‘1’ 0 = Pin is at logic ‘0’ bit 0 QEA: Status of QEAx Input Pin After Polarity Control and SWPAB Pin Swapping bit 1 = Pin is at logic ‘1’ 0 = Pin is at logic ‘0’ DS70000689D-page 262 2013-2014
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 17-3: QEIxSTAT: QEIx STATUS REGISTER U-0 U-0 HS, R/C-0 R/W-0 HS, R/C-0 R/W-0 HS, R/C-0 R/W-0 — — PCHEQIRQ PCHEQIEN PCLEQIRQ PCLEQIEN POSOVIRQ POSOVIEN bit 15 bit 8 HS, R/C-0 PCIIRQ (1) R/W-0 HS, R/C-0 R/W-0 HS, R/C-0 R/W-0 HS, R/C-0 R/W-0 PCIIEN VELOVIRQ VELOVIEN HOMIRQ HOMIEN IDXIRQ IDXIEN bit 7 bit 0 Legend: HS = Hardware Settable bit C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Va
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 17-3: QEIxSTAT: QEIx STATUS REGISTER (CONTINUED) bit 2 HOMIEN: Home Input Event Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 1 IDXIRQ: Status Flag for Index Event Status bit 1 = Index event has occurred 0 = No index event has occurred bit 0 IDXIEN: Index Input Event Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled Note 1: This status bit is only applicable to PIMOD<2:0> = 011 and 100 modes.
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 17-4: R/W-0 POSxCNTH: POSITION COUNTER x HIGH WORD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 POSCNT<31:24> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 POSCNT<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown POSCNT<31:16>: High Word Used to Form 32-Bit Position Counter x Register (POSxCNT) bi
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 17-6: R/W-0 POSxHLD: POSITION COUNTER x HOLD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 POSHLD<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 POSHLD<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown POSHLD<15:0>: Holding Register for Reading and Writing POSxCNT bits REGISTER 17-7: R/W-0 VEL
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 17-8: R/W-0 INDXxCNTH: INDEX COUNTER x HIGH WORD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INDXCNT<31:24> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INDXCNT<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown INDXCNT<31:16>: High Word Used to Form 32-Bit Index Counter x Register (INDXxCNT) bit
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 17-10: INDXxHLD: INDEX COUNTER x HOLD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INDXHLD<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INDXHLD<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown INDXHLD<15:0>: Holding Register for Reading and Writing INDXxCNT bits REGISTER 17-11: QEIxIC
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 17-13: QEIxLECH: QEIx LESS THAN OR EQUAL COMPARE HIGH WORD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 QEILEC<31:24> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 QEILEC<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown QEILEC<31:16>: High Word Used to Form 32-Bit Less Than or Equal Compare
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 17-15: QEIxGECH: QEIx GREATER THAN OR EQUAL COMPARE HIGH WORD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 QEIGEC<31:24> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 QEIGEC<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown QEIGEC<31:16>: High Word Used to Form 32-Bit Greater Than or Equal C
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 17-17: INTxTMRH: INTERVAL TIMERx HIGH WORD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTTMR<31:24> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTTMR<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown INTTMR<31:16>: High Word Used to Form 32-Bit Interval Timerx Register (INTxTMR) bits R
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 17-19: INTxHLDH: INTERVAL TIMERx HOLD HIGH WORD REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTHLD<31:24> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTHLD<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown INTHLD<31:16>: Holding Register for Reading and Writing INTxTMRH bits REGISTER 17
dsPIC33EPXXXGM3XX/6XX/7XX 18.0 SERIAL PERIPHERAL INTERFACE (SPI) Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGM3XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Serial Peripheral Interface (SPI)” (DS70005185), which is available from the Microchip web site (www.microchip.com).
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 18-1: SPIx MODULE BLOCK DIAGRAM SCKx 1:1 to 1:8 Secondary Prescaler SSx/FSYNCx Sync Control Control Clock 1:1/4/16/64 Primary Prescaler Select Edge SPIxCON1<1:0> Shift Control SDOx SPIxCON1<4:2> Enable Master Clock bit 0 SDIx FP SPIxSR Transfer Transfer 8-Level FIFO Receive Buffer(1) 8-Level FIFO Transmit Buffer(1) SPIxBUF Read SPIxBUF Write SPIxBUF 16 Internal Data Bus Note 1: In Standard mode, the FIFO is only one level deep.
dsPIC33EPXXXGM3XX/6XX/7XX 18.1 1. 3. In Frame mode, if there is a possibility that the master may not be initialized before the slave: a) If FRMPOL (SPIxCON2<13>) = 1, use a pull-down resistor on SSx. b) If FRMPOL = 0, use a pull-up resistor on SSx. Note: 2. SPI Helpful Tips This insures that the first frame transmission after initialization is not shifted or corrupted. In Non-Framed 3-Wire mode (i.e., not using SSx from a master): a) If CKP (SPIxCON1<6>) = 1, always place a pull-up resistor on SSx.
dsPIC33EPXXXGM3XX/6XX/7XX 18.
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 18-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER (CONTINUED) bit 1 SPITBF: SPIx Transmit Buffer Full Status bit 1 = Transmit has not yet started, SPIxTXB is full 0 = Transmit has started, SPIxTXB is empty Standard Buffer Mode: Automatically set in hardware when the core writes to the SPIxBUF location, loading SPIxTXB. Automatically cleared in hardware when the SPIx module transfers data from SPIxTXB to SPIxSR.
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 18-2: SPIXCON1: SPIX CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DISSCK DISSDO MODE16 SMP CKE(1) bit 15 bit 8 R/W-0 R/W-0 (2) CKP SSEN R/W-0 MSTEN R/W-0 (3) SPRE2 R/W-0 (3) SPRE1 R/W-0 SPRE0 (3) R/W-0 PPRE1 (3) R/W-0 PPRE0(3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimpleme
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 18-2: SPIXCON1: SPIX CONTROL REGISTER 1 (CONTINUED) bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode)(3) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 • • • 000 = Secondary prescale 8:1 bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode)(3) 11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1 Note 1: 2: 3: The CKE bit is not used in Framed SPI modes.
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 18-3: SPIXCON2: SPIX CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 FRMEN SPIFSD FRMPOL — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — FRMDLY SPIBEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FRMEN: Framed SPIx Support bit 1 = Framed SPIx support is enabled (SSx pin is
dsPIC33EPXXXGM3XX/6XX/7XX 19.0 INTER-INTEGRATED CIRCUIT™ (I2C™) Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGM3XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Inter-Integrated Circuit™ (I2C™)” (DS70000195), which is available from the Microchip web site (www.microchip.com).
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 19-1: I2Cx BLOCK DIAGRAM (X = 1 OR 2) Internal Data Bus I2CxRCV Read SCLx/ASCLx Shift Clock I2CxRSR LSb SDAx/ASDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation Control Logic I2CxSTAT Collision Detect Read Write I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSb Read Shift Clock Reload Control BRG Down Counter Write I2CxBRG Read FP/2 DS70000689D-page
dsPIC33EPXXXGM3XX/6XX/7XX 19.
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 19-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave) Used in conjunction with the SCLREL bit. 1 = Enables software or receives clock stretching 0 = Disables software or receives clock stretching bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive) Value that is transmitted when the software initiates an Acknowledge sequence.
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 19-2: I2CxSTAT: I2Cx STATUS REGISTER R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HS R-0, HSC R-0, HSC ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 bit 15 bit 8 R/C-0, HS R/C-0, HS IWCOL I2COV R-0, HSC R/C-0, HSC D_A P R/C-0, HSC R-0, HSC R-0, HSC R-0, HSC S R_W RBF TBF bit 7 bit 0 Legend: C = Clearable bit U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit -n = Va
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 19-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware sets or clears when Start, Repeated Start or Stop is detected.
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 19-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — R/W-0 R/W-0 AMSK<9:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AMSK<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 AMSK<9:0>: Address Mask Select bits For 10-Bit
dsPIC33EPXXXGM3XX/6XX/7XX NOTES: DS70000689D-page 288 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX 20.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGM3XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Universal Asynchronous Receiver Transmitter (UART)” (DS70000582), which is available from the Microchip web site (www.microchip.com).
dsPIC33EPXXXGM3XX/6XX/7XX 20.1 1. UART Helpful Tips In multi-node direct connect UART networks, UART receive inputs react to the complementary logic level defined by the URXINV bit (UxMODE<4>), which defines the Idle state, the default of which is logic high (i.e., URXINV = 0).
dsPIC33EPXXXGM3XX/6XX/7XX 20.
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 20-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 5 ABAUD: Auto-Baud Enable bit 1 = Enables baud rate measurement on the next character – requires reception of a Sync field (55h) before other data; cleared in hardware upon completion 0 = Baud rate measurement is disabled or has completed bit 4 URXINV: UARTx Receive Polarity Inversion bit 1 = UxRX Idle state is ‘0’ 0 = UxRX Idle state is ‘1’ bit 3 BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit per
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 20-2: R/W-0 UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 UTXISEL1 UTXINV R/W-0 UTXISEL0 U-0 — R/W-0, HC UTXBRK R/W-0 (1) UTXEN R-0 R-1 UTXBF TRMT bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-1 R-0 R-0 R/C-0 R-0 URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA bit 7 bit 0 Legend: C = Clearable bit HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is c
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 20-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1) 1 = Address Detect mode is enabled; if 9-bit mode is not selected, this does not take effect 0 = Address Detect mode is disabled bit 4 RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Receiver is active bit 3 PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character (character at t
dsPIC33EPXXXGM3XX/6XX/7XX 21.0 CONTROLLER AREA NETWORK (CAN) MODULE (dsPIC33EPXXXGM6XX/7XX DEVICES ONLY) Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGM3XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Enhanced Controller Area Network (ECAN™)” (DS70353), which is available from the Microchip web site (www.microchip.com).
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 21-1: CANx MODULE BLOCK DIAGRAM RxF15 Filter RxF14 Filter RxF13 Filter RxF12 Filter DMA Controller RxF11 Filter RxF10 Filter RxF9 Filter RxF8 Filter TRB7 TX/RX Buffer Control Register RxF7 Filter TRB6 TX/RX Buffer Control Register RxF6 Filter TRB5 TX/RX Buffer Control Register RxF5 Filter TRB4 TX/RX Buffer Control Register RxF4 Filter TRB3 TX/RX Buffer Control Register RxF3 Filter TRB2 TX/RX Buffer Control Register RxF2 Filter RxM2 Mask TRB1 TX/RX Buffer Cont
dsPIC33EPXXXGM3XX/6XX/7XX 21.
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 21-2: CxCTRL2: CANx CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 — — — R-0 R-0 R-0 R-0 R-0 DNCNT<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 DNCNT<4:0>: DeviceNet™ Filter Bit Number bits 10010-11111 = Invalid selection 10001 = Compare up
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 21-3: CxVEC: CANx INTERRUPT CODE REGISTER U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0 — — — FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 bit 15 bit 8 U-0 R-1 R-0 R-0 R-0 R-0 R-0 R-0 — ICODE6 ICODE5 ICODE4 ICODE3 ICODE2 ICODE1 ICODE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 FILHIT<4:0>: Filter Hit
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 21-4: R/W-0 DMABS2 bit 15 CxFCTRL: CANx FIFO CONTROL REGISTER R/W-0 DMABS1 R/W-0 DMABS0 U-0 — U-0 — U-0 — U-0 — R/W-0 FSA4 R/W-0 FSA3 bit 7 Legend: R = Readable bit -n = Value at POR bit 12-5 bit 4-0 U-0 — U-0 — bit 8 U-0 — bit 15-13 U-0 — W = Writable bit ‘1’ = Bit is set R/W-0 FSA2 R/W-0 FSA1 R/W-0 FSA0 bit 0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown DMABS<2:0>: DMA Buffer Size bits 111 = Reserved 110 = 32 buffers in
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 21-5: CxFIFO: CANx FIFO STATUS REGISTER U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0 — — FBP5 FBP4 FBP3 FBP2 FBP1 FBP0 bit 15 bit 8 U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0 — — FNRB5 FNRB4 FNRB3 FNRB2 FNRB1 FNRB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 FBP<5:0>: FIFO Buffer Pointer bits 011111 = RB31
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 21-6: CxINTF: CANx INTERRUPT FLAG REGISTER U-0 — bit 15 U-0 — R-0 TXBO R-0 TXBP R-0 RXBP R-0 TXWAR R-0 RXWAR R-0 EWARN bit 8 R/C-0 IVRIF bit 7 R/C-0 WAKIF R/C-0 ERRIF U-0 — R/C-0 FIFOIF R/C-0 RBOVIF R/C-0 RBIF R/C-0 TBIF bit 0 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 C = Writable bit, but only ‘0’ can be written to clear the bit W = Writable bit U = Unimplem
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 21-6: bit 1 CxINTF: CANx INTERRUPT FLAG REGISTER (CONTINUED) RBIF: RX Buffer Interrupt Flag bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred TBIF: TX Buffer Interrupt Flag bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 REGISTER 21-7: CxINTE: CANx INTERRUPT ENABLE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 21-8: CxEC: CANx TRANSMIT/RECEIVE ERROR COUNT REGISTER R-0 R-0 TERRCNT7 TERRCNT6 R-0 R-0 R-0 TERRCNT5 TERRCNT4 TERRCNT3 R-0 R-0 R-0 TERRCNT2 TERRCNT1 TERRCNT0 bit 15 bit 8 R-0 R-0 RERRCNT7 RERRCNT6 R-0 R-0 R-0 RERRCNT5 RERRCNT4 RERRCNT3 R-0 RERRCNT2 R-0 R-0 RERRCNT1 RERRCNT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 TERRCNT<
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 21-10: CxCFG2: CANx BAUD RATE CONFIGURATION REGISTER 2 U-0 R/W-x U-0 U-0 U-0 R/W-x R/W-x R/W-x — WAKFIL — — — SEG2PH2 SEG2PH1 SEG2PH0 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SEG2PHTS SAM SEG1PH2 SEG1PH1 SEG1PH0 PRSEG2 PRSEG1 PRSEG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimpleme
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 21-11: CxFEN1: CANx ACCEPTANCE FILTER ENABLE REGISTER 1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLTEN<15:8> bit 15 bit 8 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLTEN<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown FLTEN<15:0>: Enable Filter n to Accept Messages bits 1 = Enables Filter n 0 = Disables F
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 21-13: CxBUFPNT2: CANx FILTERS 4-7 BUFFER POINTER REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F7BP3 F7BP2 F7BP1 F7BP0 F6BP3 F6BP2 F6BP1 F6BP0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F5BP3 F5BP2 F5BP1 F5BP0 F4BP3 F4BP2 F4BP1 F4BP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 21-15: CxBUFPNT4: CANx FILTERS 12-15 BUFFER POINTER REGISTER 4 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F15BP3 F15BP2 F15BP1 F15BP0 F14BP3 F14BP2 F14BP1 F14BP0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F13BP3 F13BP2 F13BP1 F13BP0 F12BP3 F12BP2 F12BP1 F12BP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bi
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 21-16: CxRXFnSID: CANx ACCEPTANCE FILTER n STANDARD IDENTIFIER REGISTER (n = 0-15) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 15 bit 8 R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x SID2 SID1 SID0 — EXIDE — EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 21-18: CxFMSKSEL1: CANx FILTERS 7-0 MASK SELECTION REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F7MSK1 F7MSK0 F6MSK1 F6MSK0 F5MSK1 F5MSK0 F4MSK1 F4MSK0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F3MSK1 F3MSK0 F2MSK1 F2MSK0 F1MSK1 F1MSK0 F0MSK1 F0MSK0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 21-19: CxFMSKSEL2: CANx FILTERS 15-8 MASK SELECTION REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F15MSK1 F15MSK0 F14MSK1 F14MSK0 F13MSK1 F13MSK0 F12MSK1 F12MSK0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 F11MSK1 F11MSK0 F10MSK1 F10MSK0 F9MSK1 F9MSK0 F8MSK1 F8MSK0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cle
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 21-20: CxRXMnSID: CANx ACCEPTANCE FILTER MASK n STANDARD IDENTIFIER REGISTER (n = 0-2) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 bit 15 bit 8 R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x SID2 SID1 SID0 — MIDE — EID17 EID16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown b
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 21-22: CxRXFUL1: CANx RECEIVE BUFFER FULL REGISTER 1 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXFUL<15:8> bit 15 bit 8 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXFUL<7:0> bit 7 bit 0 Legend: C = Writable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown RXFUL<15:0>: Receive Buffe
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 21-24: CxRXOVF1: CANx RECEIVE BUFFER OVERFLOW REGISTER 1 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXOVF<15:8> bit 15 bit 8 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0 RXOVF<7:0> bit 7 bit 0 Legend: C = Writable bit, but only ‘0’ can be written to clear the bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown RXOVF<15:0>: Receive B
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 21-26: CxTRmnCON: CANx TX/RX BUFFER mn CONTROL REGISTER (m = 0,2,4,6; n = 1,3,5,7) R/W-0 R-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 TXENn TXABTn TXLARBn TXERRn TXREQn RTRENn TXnPRI1 TXnPRI0 bit 15 bit 8 R/W-0 R-0 TXENm TXABTm(1) R-0 R-0 TXLARBm(1) TXERRm(1) R/W-0 R/W-0 R/W-0 R/W-0 TXREQm RTRENm TXmPRI1 TXmPRI0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bi
dsPIC33EPXXXGM3XX/6XX/7XX 21.4 CAN Message Buffers CAN Message Buffers are part of RAM memory. They are not CAN Special Function Registers. The user application must directly write into the RAM area that is configured for CAN Message Buffers. The location and size of the buffer area is defined by the user application.
dsPIC33EPXXXGM3XX/6XX/7XX ( BUFFER 21-3: CANx MESSAGE BUFFER WORD 2 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID5 EID4 EID3 EID2 EID1 EID0 RTR RB1 bit 15 bit 8 U-x U-x U-x R/W-x R/W-x R/W-x R/W-x R/W-x — — — RB0 DLC3 DLC2 DLC1 DLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-10 EID<5:0>: Extended Identifier bits bit 9 RTR: Remote Transmission Requ
dsPIC33EPXXXGM3XX/6XX/7XX BUFFER 21-5: R/W-x CANx MESSAGE BUFFER WORD 4 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 3<15:8> bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 2<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Byte 3<15:8>: CANx Message Byte 3 bit 7-0 Byte 2<7:0>: CANx Message Byte 2 BUFFER 21-6: R/W-x x = Bit is unknown CANx MESSAGE
dsPIC33EPXXXGM3XX/6XX/7XX BUFFER 21-7: R/W-x CANx MESSAGE BUFFER WORD 6 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 7<15:8> bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x Byte 6<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Byte 7<15:8>: CANx Message Byte 7 bit 7-0 Byte 6<7:0>: CANx Message Byte 6 BUFFER 21-8: x = Bit is unknown CANx MESSAGE BUFFER
dsPIC33EPXXXGM3XX/6XX/7XX NOTES: DS70000689D-page 320 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX 22.0 CHARGE TIME MEASUREMENT UNIT (CTMU) Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGM3XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Charge Time Measurement Unit (CTMU)” (DS70661), which is available on the Microchip web site (www.microchip.com).
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 22-1: CTMU BLOCK DIAGRAM CTMUCON1 or CTMUCON2 CTMUICON ITRIM<5:0> IRNG<1:0> Current Source Edge Control Logic CTED1 CTED2 EDG1STAT EDG2STAT Timer1 OC1 IC1 CMP1 Current Control TGEN CTMU Control Logic Pulse Generator CTMUI to ADCx Analog-to-Digital Trigger CTPLS CTMUP CTMU TEMP CTMU Temperature Sensor C1IN1CDelay CMP1 External Capacitor for Pulse Generation Current Control Selection CTMU TEMP DS70000689D-page 322 TGEN EDG1STAT, EDG2STAT 0 EDG1STAT = EDG2S
dsPIC33EPXXXGM3XX/6XX/7XX 22.
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 22-2: CTMUCON2: CTMU CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EDG1MOD EDG1POL EDG1SEL3 EDG1SEL2 EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 EDG2MOD EDG2POL EDG2SEL3 EDG2SEL2 EDG2SEL1 EDG2SEL0 — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknow
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 22-2: CTMUCON2: CTMU CONTROL REGISTER 2 (CONTINUED) bit 5-2 EDG2SEL<3:0>: Edge 2 Source Select bits 1111 = FOSC 1110 = OSCI pin 1101 = FRC oscillator 1100 = Reserved 1011 = Internal LPRC oscillator 1010 = Reserved 100x = Reserved 0111 = Reserved 0110 = Reserved 0101 = Reserved 0100 = CMP1 module(1) 0011 = CTED2 pin 0010 = CTED1 pin 0001 = OC1 module 0000 = IC1 module bit 1-0 Unimplemented: Read as ‘0’ Note 1: If the TGEN bit is set to ‘1’, then the CMP1 module shoul
dsPIC33EPXXXGM3XX/6XX/7XX CTMUICON: CTMU CURRENT CONTROL REGISTER(3) REGISTER 22-3: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-10 ITRIM<5:0>: Current Source Trim bits 011111 = Maximum positive cha
dsPIC33EPXXXGM3XX/6XX/7XX 23.0 10-BIT/12-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGM3XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Analog-to-Digital Converter (ADC)” (DS70621), which is available from the Microchip web site (www.microchip.com).
ADCx MODULE BLOCK DIAGRAM WITH CONNECTION OPTIONS FOR ANx PINS AND OP AMPS This diagram depicts all of the available ADCx connection options to the four S&H amplifiers, which are designated: CH0, CH1, CH2 and CH3. The ANx analog pins or op amp outputs are connected to the CH0-CH3 amplifiers through the multiplexers, controlled by the SFR control bits, CH0Sx, CH0Nx, CH123Sx and CH123Nx.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 23-2: ADCx CONVERSION CLOCK PERIOD BLOCK DIAGRAM AD1CON3<15> ADCx Internal RC Clock(2) 1 TAD AD1CON3<7:0> 0 6 TP(1) ADCx Conversion Clock Multiplier 1, 2, 3, 4, 5,..., 256 Note 1: 2: TP = 1/FP. See the ADCx electrical specifications in Section 33.0 “Electrical Characteristics” for the exact RC clock value. 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX 23.2 1. 2. ADCx Helpful Tips The SMPIx control bits in the ADxCON2 registers: a) Determine when the ADCx interrupt flag is set and an interrupt is generated, if enabled. b) When the CSCNA bit in the ADxCON2 register is set to ‘1’, this determines when the ADCx analog scan channel list, defined in the AD1CSSL/AD1CSSH registers, starts over from the beginning.
dsPIC33EPXXXGM3XX/6XX/7XX 23.
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 23-1: ADxCON1: ADCx CONTROL REGISTER 1 (CONTINUED) bit 7-5 SSRC<2:0>: Sample Clock Source Select bits If SSRCG = 1: 111 = Reserved 110 = PTGO15 primary trigger compare ends sampling and starts conversion(1) 101 = PTGO14 primary trigger compare ends sampling and starts conversion(1) 100 = PTGO13 primary trigger compare ends sampling and starts conversion(1) 011 = PTGO12 primary trigger compare ends sampling and starts conversion(1) 010 = PWM Generator 3 primary trigger c
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 23-2: ADxCON2: ADCx CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 VCFG2(1) VCFG1(1) VCFG0(1) OFFCAL — CSCNA CHPS1 CHPS0 bit 15 bit 8 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUFS SMPI4 SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-13 x = Bit is unknown VCFG<2:0>: Con
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 23-2: ADxCON2: ADCx CONTROL REGISTER 2 (CONTINUED) bit 6-2 SMPI<4:0>: Increment Rate bits When ADDMAEN = 0: x1111 = Generates interrupt after completion of every 16th sample/conversion operation x1110 = Generates interrupt after completion of every 15th sample/conversion operation • • • x0001 = Generates interrupt after completion of every 2nd sample/conversion operation x0000 = Generates interrupt after completion of every sample/conversion operation When ADDMAEN = 1:
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 23-3: R/W-0 ADxCON3: ADCx CONTROL REGISTER 3 U-0 ADRC U-0 — — R/W-0 SAMC4 (1) R/W-0 (1) SAMC3 R/W-0 (1) SAMC2 R/W-0 SAMC1 (1) R/W-0 SAMC0(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCS7(2) ADCS6(2) ADCS5(2) ADCS4(2) ADCS3(2) ADCS2(2) ADCS1(2) ADCS0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ADRC: ADC
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 23-4: ADxCON4: ADCx CONTROL REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — ADDMAEN bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — DMABL2 DMABL1 DMABL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8 ADDMAEN: ADCx DMA Enable bit 1 = Conversion re
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 23-5: ADxCHS123: ADCx INPUT CHANNEL 1, 2, 3 SELECT REGISTER U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — CH123SB2 CH123SB1 CH123NB1 CH123NB0 CH123SB0 bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — CH123SA2 CH123SA1 CH123NA1 CH123NA0 CH123SA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 23-6: ADxCHS0: ADCx INPUT CHANNEL 0 SELECT REGISTER(3) R/W-0 CH0NB bit 15 U-0 — R/W-0 R/W-0 CH0SB5(1,4,5) CH0SB4(1,5) R/W-0 CH0SB3(1,5) R/W-0 CH0SB2(1,5) R/W-0 CH0SB1(1,5) R/W-0 CH0SB0(1,5) bit 8 R/W-0 CH0NA bit 7 U-0 — R/W-0 R/W-0 CH0SA5(1,4,5) CH0SA4(1,5) R/W-0 CH0SA3(1,5) R/W-0 CH0SA2(1,5) R/W-0 CH0SA1(1,5) R/W-0 CH0SA0(1,5) bit 0 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13-8 Note 1: 2: 3: 4: 5: W = Writable bit ‘1’ = Bit is set U
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 23-6: bit 7 ADxCHS0: ADCx INPUT CHANNEL 0 SELECT REGISTER(3) (CONTINUED) CH0NA: Channel 0 Negative Input Select for Sample MUXA bit 1 = Channel 0 negative input is AN1(1) 0 = Channel 0 negative input is VREFL Unimplemented: Read as ‘0’ CH0SA<5:0>: Channel 0 Positive Input Select for Sample MUXA bits(1,4,5) 111111 = Channel 0 positive input is (AN63) unconnected 111110 = Channel 0 positive input is (AN62) the CTMU temperature voltage 111101 = Channel 0 positive input is (
dsPIC33EPXXXGM3XX/6XX/7XX ADxCSSH: ADCx INPUT SCAN SELECT REGISTER HIGH(2) REGISTER 23-7: R/W-0 R/W-0 CSS31 CSS30 R/W-0 CSS29 R/W-0 CSS28 R/W-0 CSS27 R/W-0 (1) CSS26 R/W-0 (1) CSS25 R/W-0 CSS24(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSS23 CSS22 CSS21 CSS20 CSS19 CSS18 CSS17 CSS16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 CSS31: ADCx In
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 23-7: ADxCSSH: ADCx INPUT SCAN SELECT REGISTER HIGH(2) (CONTINUED) bit 4 CSS20: ADCx Input Scan Selection bit 1 = Selects ANx for input scan 0 = Skips ANx for input scan bit 3 CSS19: ADCx Input Scan Selection bit 1 = Selects ANx for input scan 0 = Skips ANx for input scan bit 2 CSS18: ADCx Input Scan Selection bit 1 = Selects ANx for input scan 0 = Skips ANx for input scan bit 1 CSS17: ADCx Input Scan Selection bit 1 = Selects ANx for input scan 0 = Skips ANx for
dsPIC33EPXXXGM3XX/6XX/7XX ADxCSSL: ADCx INPUT SCAN SELECT REGISTER LOW(1,2) REGISTER 23-8: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSS<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSS<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 Note 1: 2: x = Bit is unknown CSS<15:0>: ADCx Input Scan Selection bits 1 = Selects ANx for input scan 0 = Sk
dsPIC33EPXXXGM3XX/6XX/7XX 24.0 DATA CONVERTER INTERFACE (DCI) MODULE 24.1 The Data Converter Interface (DCI) module allows simple interfacing of devices, such as audio coder/ decoders (Codecs), ADC and D/A Converters. The following interfaces are supported: Note 1: This data sheet is not intended to be a comprehensive reference source.
dsPIC33EPXXXGM3XX/6XX/7XX 24.
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 24-2: DCICON2: DCI CONTROL REGISTER 2 r-0 r-0 r-0 r-0 R/W-0 R/W-0 r-0 R/W-0 r r r r BLEN1 BLEN0 r COFSG3 bit 15 bit 8 R/W-0 R/W-0 R/W-0 r-0 R/W-0 R/W-0 R/W-0 R/W-0 COFSG2 COFSG1 COFSG0 r WS3 WS2 WS1 WS0 bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Reserved: Read as ‘0’ bit 11-10 BLEN<1:0>: Buffer Len
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 24-3: DCICON3: DCI CONTROL REGISTER 3 r-0 r-0 r-0 r-0 r r r r R/W-0 R/W-0 R/W-0 R/W-0 BCG<11:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BCG<7:0> bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Reserved: Read as ‘0’ bit 11-0 BCG<11:0>: DCI Bit Clock Generator Control bits DS70000689D-page 346
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 24-4: DCISTAT: DCI STATUS REGISTER r-0 r-0 r-0 r-0 R-0 R-0 R-0 R-0 r r r r SLOT3 SLOT2 SLOT1 SLOT0 bit 15 bit 8 r-0 r-0 r-0 r-0 R-0 R-0 R-0 R-0 r r r r ROV RFUL TUNF TMPTY bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Reserved: Read as ‘0’ bit 11-8 SLOT<3:0>: DCI Slot Status bits 1111 = Slot 15 is curr
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 24-5: R/W-0 RSCON: DCI RECEIVE SLOT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RSE<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RSE<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown RSE<15:0>: DCI Receive Slot Enable bits 1 = CSDI data is received during Individual Time Slot n 0 = C
dsPIC33EPXXXGM3XX/6XX/7XX 25.0 PERIPHERAL TRIGGER GENERATOR (PTG) MODULE Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGM3XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Peripheral Trigger Generator (PTG)” (DS70669), which is available from the Microchip web site (www.microchip.com).
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 25-1: PTG BLOCK DIAGRAM PTGHOLD PTGL0<15:0> PTGADJ Step Command PTGTxLIM<15:0> PTG General Purpose Timerx PTGCxLIM<15:0> PTGSDLIM<15:0> PTG Step Delay Timer PTG Loop Counter x PTGBTE<15:0> PTGCST<15:0> Step Command PTGCON<15:0> Trigger Outputs PTGDIV<4:0> FP TAD T1CLK T2CLK T3CLK FOSC Clock Inputs 16-Bit Data Bus PTGCLK<2:0> PTG Control Logic Step Command Trigger Inputs PTG Interrupts Step Command PWM OC1 OC2 IC1 CMPx ADC INT2 PTGO0 • • • PTGO31 PTG0I
dsPIC33EPXXXGM3XX/6XX/7XX 25.
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 25-1: bit 1-0 Note 1: 2: PTGCST: PTG CONTROL/STATUS REGISTER (CONTINUED) PTGITM<1:0>: PTG Input Trigger Command Operating Mode bits(1) 11 = Single level detect with step delay is not executed on exit of command (regardless of PTGCTRL command) 10 = Single level detect with step delay is executed on exit of command 01 = Continuous edge detect with step delay is not executed on exit of command (regardless of PTGCTRL command) 00 = Continuous edge detect with step delay is e
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 25-2: PTGCON: PTG CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTGCLK2 PTGCLK1 PTGCLK0 PTGDIV4 PTGDIV3 PTGDIV2 PTGDIV1 PTGDIV0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 PTGPWD3 PTGPWD2 PTGPWD1 PTGPWD0 — PTGWDT2 PTGWDT1 PTGWDT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-13 PTGCLK<2:0>:
dsPIC33EPXXXGM3XX/6XX/7XX PTGBTE: PTG BROADCAST TRIGGER ENABLE REGISTER(1,2) REGISTER 25-3: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCTS4 ADCTS3 ADCTS2 ADCTS1 IC4TSS IC3TSS IC2TSS IC1TSS bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OC4CS OC3CS OC2CS OC1CS OC4TSS OC3TSS OC2TSS OC1TSS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unkn
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 25-3: PTGBTE: PTG BROADCAST TRIGGER ENABLE REGISTER(1,2) (CONTINUED) bit 4 OC1CS: Clock Source for OC1 bit 1 = Generates clock pulse when the broadcast command is executed 0 = Does not generate clock pulse when the broadcast command is executed bit 3 OC4TSS: Trigger/Synchronization Source for OC4 bit 1 = Generates trigger/synchronization when the broadcast command is executed 0 = Does not generate trigger/synchronization when the broadcast command is executed bit 2
dsPIC33EPXXXGM3XX/6XX/7XX PTGT0LIM: PTG TIMER0 LIMIT REGISTER(1) REGISTER 25-4: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTGT0LIM<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTGT0LIM<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 Note 1: x = Bit is unknown PTGT0LIM<15:0>: PTG Timer0 Limit Register bits General purpose Timer0 Limit registe
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 25-6: R/W-0 PTGSDLIM: PTG STEP DELAY LIMIT REGISTER(1,2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTGSDLIM<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTGSDLIM<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 Note 1: 2: x = Bit is unknown PTGSDLIM<15:0>: PTG Step Delay Limit Register bits Holds a PTG step delay v
dsPIC33EPXXXGM3XX/6XX/7XX PTGC1LIM: PTG COUNTER 1 LIMIT REGISTER(1) REGISTER 25-8: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTGC1LIM<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTGC1LIM<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 Note 1: x = Bit is unknown PTGC1LIM<15:0>: PTG Counter 1 Limit Register bits May be used to specify the loo
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 25-10: PTGADJ: PTG ADJUST REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTGADJ<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTGADJ<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 Note 1: x = Bit is unknown PTGADJ<15:0>: PTG Adjust Register bits This register holds user-supplied data to be added to th
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 25-12: PTGQPTR: PTG STEP QUEUE POINTER REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTGQPTR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 PTGQPTR<4:0>: PTG Step Queue Pointer Register bits Thi
dsPIC33EPXXXGM3XX/6XX/7XX 25.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 25-1: bit 3-0 PTG STEP COMMAND FORMAT (CONTINUED) Step Command OPTION<3:0> PTGCTRL(1) 0000 Reserved 0001 Reserved 0010 Disable Step Delay Timer (PTGSD) 0011 Reserved 0100 Reserved 0101 Reserved 0110 Enable Step Delay Timer (PTGSD) 0111 Reserved 1000 Start and wait for the PTG Timer0 to match Timer0 Limit register PTGADD(1) PTGCOPY(1) Note 1: 2: Option Description 1001 Start and wait for the PTG Timer1 to match Timer1 Limit register 1010 Reserved
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 25-1: bit 3-0 PTG STEP COMMAND FORMAT (CONTINUED) Step Command PTGWHI(1) or PTGWLO(1) PTGIRQ(1) OPTION<3:0> 0000 PWM Special Event Trigger 0001 PWM master time base synchronization output 0010 PWM1 interrupt 0011 PWM2 interrupt 0100 PWM3 interrupt 0101 PWM4 interrupt 0110 PWM5 interrupt 0111 OC1 Trigger Event 1000 OC2 Trigger Event 1001 IC1 Trigger Event 1010 CMP1 Trigger Event 1011 CMP2 Trigger Event 1100 CMP3 Trigger Event 1101 CMP4 Trigger Ev
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 25-2: PTG OUTPUT DESCRIPTIONS PTG Output Number PTG Output Description PTGO0 Trigger/Synchronization Source for OC1 PTGO1 Trigger/Synchronization Source for OC2 PTGO2 Trigger/Synchronization Source for OC3 PTGO3 Trigger/Synchronization Source for OC4 PTGO4 Clock Source for OC1 PTGO5 Clock Source for OC2 PTGO6 Clock Source for OC3 PTGO7 Clock Source for OC4 PTGO8 Trigger/Synchronization Source for IC1 PTGO9 Trigger/Synchronization Source for IC2 PTGO10
dsPIC33EPXXXGM3XX/6XX/7XX 26.0 OP AMP/COMPARATOR MODULE Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGM3XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Op Amp/ Comparator” (DS70000357), which is available from the Microchip web site (www.microchip.com).
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 26-2: OP AMP/COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM VREFSEL (CVR1CON<10>) AVDD CVRSS = 1 (CVR1CON<4>) CVRSRC 1 CVR1CON<3:0> CVRSS = 0 8R (CVR1CON<4>) CVREN (CVR1CON<7>) CVREFIN CVR3 CVR2 CVR1 CVR0 VREF+ 0 R CVRR1 (CVR1CON<11>) R R 16-to-1 MUX R 16 Steps R CVREF1O CVROE (CVR1CON<6>) R VREFSEL (CVR2CON<10>) R CVRR0 (CVR1CON<5>) 8R 0 AVSS AVDD CVRSS = 1 (CVR2CON<4>) CVRSRC CVR2CON<3:0> CVRSS = 0 8R (CVR2CON<4>) CVREN (CVR2CON<4>) CVR3 CVR2
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 26-3: USER-PROGRAMMABLE BLANKING FUNCTION BLOCK DIAGRAM SELSRCA<3:0> (CMxMSKSRC<3:0>) MUX A Comparator Output Blanking Signals MAI “AND-OR” Function MAI MBI Blanking Logic To Digital Filter ANDI AND SELSRCB<3:0> (CMxMSKSRC<7:4) MCI MUX B MAI Blanking Signals MBI MBI OR MASK HLMS (CMxMSKCON<15) MCI SELSRCC<3:0> (CMxMSKSRC<11:8) MUX C CMxMSKCON Blanking Signals FIGURE 26-4: MCI DIGITAL FILTER INTERCONNECT BLOCK DIAGRAM TxCLK(1,2) 1xx SYNCO1(3) 010
dsPIC33EPXXXGM3XX/6XX/7XX 26.1 26.1.1 Op Amp Application Considerations Figure 26-5 shows a typical inverting amplifier circuit taking advantage of the internal connections from the op amp output to the input of the ADCx. The advantage of this configuration is that the user does not need to consume another analog input (ANy) on the device, and allows the user to simultaneously sample all three op amps with the ADCx module, if needed.
dsPIC33EPXXXGM3XX/6XX/7XX 26.1.2 OP AMP CONFIGURATION B 26.2 Figure 26-6 shows a typical inverting amplifier circuit with the output of the op amp (OAxOUT) externally routed to a separate analog input pin (ANy) on the device. This op amp configuration is slightly different in terms of the op amp output and the ADCx input connection, therefore, RINT1 is not included in the transfer function.
dsPIC33EPXXXGM3XX/6XX/7XX 26.
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 26-2: R/W-0 CMxCON: OP AMP/COMPARATOR x CONTROL REGISTER (x = 1, 2, 3 OR 5) R/W-0 CON COE R/W-0 U-0 U-0 — CPOL — R/W-0 R/W-0 (2) OPMODE CEVT (3) R/W-0 COUT bit 15 bit 8 R/W-0 EVPOL1 R/W-0 (3) EVPOL0(3) U-0 R/W-0 — CREF(1) U-0 — U-0 R/W-0 R/W-0 — CCH1(1) CCH0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CO
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 26-2: CMxCON: OP AMP/COMPARATOR x CONTROL REGISTER (x = 1, 2, 3 OR 5) (CONTINUED) bit 7-6 EVPOL<1:0>: Trigger/Event/Interrupt Polarity Select bits(3) 11 = Trigger/event/interrupt generated on any change of the comparator output (while CEVT = 0) 10 = Trigger/event/interrupt generated only on high-to-low transition of the polarity selected comparator output (while CEVT = 0) If CPOL = 1 (inverted polarity): Low-to-high transition of the comparator output.
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 26-3: R/W-0 CM4CON: OP AMP/COMPARATOR 4 CONTROL REGISTER R/W-0 CON R/W-0 COE CPOL U-0 U-0 — — U-0 — R/W-0 CEVT (2) R/W-0 COUT bit 15 bit 8 R/W-0 EVPOL1 R/W-0 (2) U-0 (2) EVPOL0 — R/W-0 U-0 (1) CREF — U-0 — R/W-0 CCH1 (1) R/W-0 CCH0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CON: Op Amp/Comparator Enable b
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 26-3: CM4CON: OP AMP/COMPARATOR 4 CONTROL REGISTER (CONTINUED) bit 7-6 EVPOL<1:0>: Trigger/Event/Interrupt Polarity Select bits(2) 11 = Trigger/event/interrupt generated on any change of the comparator output (while CEVT = 0) 10 = Trigger/event/interrupt generated only on high-to-low transition of the polarity selected comparator output (while CEVT = 0) If CPOL = 1 (inverted polarity): Low-to-high transition of the comparator output.
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 26-4: CMxMSKSRC: COMPARATOR x MASK SOURCE SELECT CONTROL REGISTER U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 RW-0 — — — — SELSRCC3 SELSRCC2 SELSRCC1 SELSRCC0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 SELSRCB3 SELSRCB2 SELSRCB1 R/W-0 R/W-0 SELSRCB0 SELSRCA3 R/W-0 R/W-0 R/W-0 SELSRCA2 SELSRCA1 SELSRCA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 26-4: bit 3-0 CMxMSKSRC: COMPARATOR x MASK SOURCE SELECT CONTROL REGISTER (CONTINUED) SELSRCA<3:0>: Mask A Input Select bits 1111 = FLT4 1110 = FLT2 1101 = PTGO19 1100 = PTGO18 1011 = PWM6H 1010 = PWM6L 1001 = PWM5H 1000 = PWM5L 0111 = PWM4H 0110 = PWM4L 0101 = PWM3H 0100 = PWM3L 0011 = PWM2H 0010 = PWM2L 0001 = PWM1H 0000 = PWM1L DS70000689D-page 376 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 26-5: CMxMSKCON: COMPARATOR x MASK GATING CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 HLMS: High
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 26-5: CMxMSKCON: COMPARATOR x MASK GATING CONTROL REGISTER (CONTINUED) bit 3 ABEN: AND Gate B Input Enable bit 1 = MBI is connected to the AND gate 0 = MBI is not connected to the AND gate bit 2 ABNEN: AND Gate B Input Inverted Enable bit 1 = Inverted MBI is connected to the AND gate 0 = Inverted MBI is not connected to the AND gate bit 1 AAEN: AND Gate A Input Enable bit 1 = MAI is connected to the AND gate 0 = MAI is not connected to the AND gate bit 0 AANEN: AN
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 26-6: CMxFLTR: COMPARATOR x FILTER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CFSEL2 CFSEL1 CFSEL0 CFLTREN CFDIV2 CFDIV1 CFDIV0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 CFSEL<2:0>: Comparator Filter
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 26-7: CVR1CON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER 1 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0 — — — — CVRR1 VREFSEL — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE CVRR0 CVRSS CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 26-8: CVR2CON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER 2 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0 — — — — CVRR1 VREFSEL — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE CVRR0 CVRSS CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’
dsPIC33EPXXXGM3XX/6XX/7XX NOTES: DS70000689D-page 382 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX 27.0 REAL-TIME CLOCK AND CALENDAR (RTCC) Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGM3XX/6XX/7XX families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Real-Time Clock and Calendar (RTCC)” (DS70584), which is available from the Microchip web site (www.microchip.com).
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 27-1: RTCC BLOCK DIAGRAM RTCPTR<1:0> dsPIC33EPXXXGM RTCC Timer CAL<7:0> SOSCO 32.
dsPIC33EPXXXGM3XX/6XX/7XX 27.1 Note: Writing to the RTCC Timer To allow the RTCC module to be clocked by the secondary crystal oscillator, the Secondary Oscillator Enable (LPOSCEN) bit in the Oscillator Control (OSCCON<1>) register must be set. For further details, refer to the “dsPIC33/ PIC24 Family Reference Manual”, “Oscillator” (DS70580). The user application can configure the time and calendar by writing the desired seconds, minutes, hours, weekday, date, month and year to the RTCC registers.
dsPIC33EPXXXGM3XX/6XX/7XX 27.
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 27-2: PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — RTSECSEL(1) PMPTTL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-2 Unimplemented: Read as ‘0’ bit 1 RTSECSEL: RTCC Seconds Clock Output Select bit(1) 1 = RTCC second
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 27-3: ALCFGRPT: ALARM CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 27-4: RTCVAL (WHEN RTCPTR<1:0> = 11): YEAR VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x YRTEN3 YRTEN2 YRTEN1 YRTEN0 YRONE3 YRONE2 YRONE1 YRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit
dsPIC33EPXXXGM3XX/6XX/7XX RTCVAL (WHEN RTCPTR<1:0> = 01): WEEKDAY AND HOURS VALUE REGISTER(1) REGISTER 27-6: U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x — — — — — WDAY2 WDAY1 WDAY0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented:
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 27-8: ALRMVAL (WHEN ALRMPTR<1:0> = 10): ALARM MONTH AND DAY VALUE REGISTER(1) U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-13 Un
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 27-9: ALRMVAL (WHEN ALRMPTR<1:0> = 01): ALARM WEEKDAY AND HOURS VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x — — — — — WDAY2 WDAY1 WDAY0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimpl
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 27-10: ALRMVAL (WHEN ALRMPTR<1:0> = 00): ALARM MINUTES AND SECONDS VALUE REGISTER U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 15 bit 8 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit
dsPIC33EPXXXGM3XX/6XX/7XX NOTES: DS70000689D-page 394 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX 28.0 PARALLEL MASTER PORT (PMP) Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGM3XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Parallel Master Port (PMP)” (DS70576), which is available from the Microchip web site (www.microchip.com).
dsPIC33EPXXXGM3XX/6XX/7XX 28.
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 28-1: PMCON: PARALLEL MASTER PORT CONTROL REGISTER(3) (CONTINUED) bit 3 CS1P: Chip Select 0 Polarity bit(1) 1 = Active-high (PMCS1/PMCS)(2) 0 = Active-low (PMCS1/PMCS) bit 2 BEP: Byte Enable Polarity bit 1 = Byte enable is active-high (PMBE) 0 = Byte enable is active-low (PMBE) bit 1 WRSP: Write Strobe Polarity bit For Slave Modes and Master Mode 2 (PMMODE<9:8> = 00, 01, 10): 1 = Write strobe is active-high (PMWR) 0 = Write strobe is active-low (PMWR) For Master Mod
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 28-2: PMMODE: PARALLEL MASTER PORT MODE REGISTER(4) R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUSY IRQM1 IRQM0 INCM1 INCM0 MODE16 MODE1 MODE0 bit 15 bit 8 R/W-0 R/W-0 WAITB1(1,2,3) WAITB0(1,2,3) R/W-0 R/W-0 R/W-0 R/W-0 WAITM3 WAITM2 WAITM1 WAITM0 R/W-0 R/W-0 WAITE1(1,2,3) WAITE0(1,2,3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at Reset ‘1’ = Bit is set ‘0’ = Bit is cleare
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 28-2: PMMODE: PARALLEL MASTER PORT MODE REGISTER(4) (CONTINUED) bit 5-2 WAITM<3:0>: Read to Byte Enable Strobe Wait State Configuration bits 1111 = Wait of additional 15 TP • • • 0001 = Wait of additional 1 TP 0000 = No additional Wait cycles (operation forced into one TP) bit 1-0 WAITE<1:0>: Data Hold After Strobe Wait State Configuration bits(1,2,3) 11 = Wait of 4 TP 10 = Wait of 3 TP 01 = Wait of 2 TP 00 = Wait of 1 TP Note 1: 2: 3: 4: The applied Wait state dep
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 28-3: PMADDR: PARALLEL MASTER PORT ADDRESS REGISTER (MASTER MODES ONLY)(1,2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CS2 CS1 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at Reset ‘1’ = Bit is set ‘0’ = Bit is cleared bit
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 28-4: PMAEN: PARALLEL MASTER PORT ADDRESS ENABLE REGISTER(1) R/W-0 R/W-0 PTEN15 PTEN14 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTEN<13:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTEN<7:2> R/W-0 PTEN<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at Reset ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PTEN15: PMCS2 Strobe Enable bit 1 = PMA15 functions as
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 28-5: PMSTAT: PARALLEL MASTER PORT STATUS REGISTER (SLAVE MODE ONLY)(1) R-0 R/W-0, HS U-0 U-0 R-0 R-0 R-0 R-0 IBF IBOV — — IB3F IB2F IB1F IB0F bit 15 bit 8 R-1 R/W-0, HS U-0 U-0 R-1 R-1 R-1 R-1 OBE OBUF — — OB3E OB2E OB1E OB0E bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at Reset ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 IB
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 28-6: PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — RTSECSEL PMPTTL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-2 x = Bit is unknown Unimplemented: Read as ‘0’ bit 1 Not used by the PMP module.
dsPIC33EPXXXGM3XX/6XX/7XX NOTES: DS70000689D-page 404 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX 29.0 The programmable CRC generator offers the following features: PROGRAMMABLE CYCLIC REDUNDANCY CHECK (CRC) GENERATOR • User-Programmable (up to 32nd order) polynomial CRC equation • Interrupt Output • Data FIFO Note 1: This data sheet summarizes the features of the dsPIC33EPXXXGM3XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 29-2: CRC SHIFT ENGINE DETAIL CRCWDATH CRCWDATL Read/Write Bus X(1)(1) Shift Buffer Data Note 1: 2: 29.1 Bit 0 X(n)(1) X(2)(1) Bit 1 Bit n(2) Bit 2 Each XOR stage of the shift engine is programmable. See text for details. Polynomial Length n is determined by ([PLEN<4:0>] + 1). Overview The CRC module can be programmed for CRC polynomials of up to the 32nd order, using up to 32 bits.
dsPIC33EPXXXGM3XX/6XX/7XX 29.
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 29-2: CRCCON2: CRC CONTROL REGISTER 2 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DWIDTH4 DWIDTH3 DWIDTH2 DWIDTH1 DWIDTH0 bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — PLEN4 PLEN3 PLEN2 PLEN1 PLEN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 DW
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 29-3: R/W-0 CRCXORH: CRC XOR POLYNOMIAL HIGH REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X<31:24> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown X<31:16>: XOR of Polynomial Term Xn Enable bits REGISTER 29-4: R/W-0 CRCXORL: CRC XOR POLYNOMIAL LO
dsPIC33EPXXXGM3XX/6XX/7XX NOTES: DS70000689D-page 410 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX 30.0 Note: SPECIAL FEATURES This data sheet summarizes the features of the dsPIC33EPXXXGM3XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section of the “dsPIC33/PIC24 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 30-1: File Name Reserved Reserved FICD FPOR FWDT FOSC FOSCSEL FGS Reserved Reserved Legend: Note 1: 2: Address CONFIGURATION BYTE REGISTER MAP Device Memory Size Bits 23-8 (Kbytes) 0157EC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 — — — — — — — — — — — — — — — — — — — Reserved(2) — JTAGEN Reserved(1) Reserved(2) — WDTWIN<1:0> ALTI2C2 ALTI2C1 BOREN — PLLKEN WDTPRE IOL1WAY — — 128 02AFEC 256 0557EC 512 0157EE 1
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 30-2: CONFIGURATION BITS DESCRIPTION Bit Field Description GCP General Segment Code-Protect bit 1 = User program memory is not code-protected 0 = Code protection is enabled for the entire program memory space GWRP General Segment Write-Protect bit 1 = User program memory is not write-protected 0 = User program memory is write-protected IESO Two-Speed Oscillator Start-up Enable bit(1) 1 = Starts up device with FRC, then automatically switches to the user-selected osci
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 30-2: CONFIGURATION BITS DESCRIPTION (CONTINUED) Bit Field Description WDTPRE Watchdog Timer Prescaler bit 1 = 1:128 0 = 1:32 WDTPOST<3:0> Watchdog Timer Postscaler bits 1111 = 1:32,768 1110 = 1:16,384 • • • 0001 = 1:2 0000 = 1:1 WDTWIN<1:0> Watchdog Timer Window Select bits 11 = WDT Window is 25% of WDT Period 10 = WDT Window is 37.
dsPIC33EPXXXGM3XX/6XX/7XX REGISTER 30-1: R DEVID: DEVICE ID REGISTER R R R R R R R DEVID<23:16>(1) bit 23 bit 16 R R R R R R R R DEVID<15:8>(1) bit 15 bit 8 R R R R R R R R DEVID<7:0>(1) bit 7 bit 0 Legend: R = Read-Only bit bit 23-0 Note 1: DEVID<23:0>: Device Identifier bits(1) Refer to the “dsPIC33E/PIC24E Flash Programming Specification for Devices with Volatile Configuration Bits” (DS70663) for the list of device ID values.
dsPIC33EPXXXGM3XX/6XX/7XX 30.2 FIGURE 30-1: User ID Words dsPIC33EPXXXGM3XX/6XX/7XX devices contain four User ID Words, located at addresses, 0x800FF8 through 0x800FFE. The User ID Words can be used for storing product information, such as serial numbers, system manufacturing dates, manufacturing lot numbers and other application-specific information. 3.3V dsPIC33EP VDD The User ID Words register map is shown in Table 30-3.
dsPIC33EPXXXGM3XX/6XX/7XX 30.5 30.5.2 Watchdog Timer (WDT) For dsPIC33EPXXXGM3XX/6XX/7XX devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. 30.5.1 PRESCALER/POSTSCALER The nominal WDT clock source from LPRC is 32 kHz. This feeds a prescaler that can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the WDTPRE Configuration bit.
dsPIC33EPXXXGM3XX/6XX/7XX 30.6 JTAG Interface dsPIC33EPXXXGM3XX/6XX/7XX devices implement a JTAG interface, which supports boundary scan device testing. Detailed information on this interface is provided in future revisions of the document. Note: 30.7 Refer to the “dsPIC33/PIC24 Family Reference Manual”, “Programming and Diagnostics” (DS70608) for further information on usage, configuration and operation of the JTAG interface.
dsPIC33EPXXXGM3XX/6XX/7XX 31.0 Note: INSTRUCTION SET SUMMARY This data sheet summarizes the features of the dsPIC33EPXXXGM3XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section of the “dsPIC33/PIC24 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com). The dsPIC33EP instruction set is almost identical to that of the dsPIC30F and dsPIC33F.
dsPIC33EPXXXGM3XX/6XX/7XX Most instructions are a single word. Certain double-word instructions are designed to provide all the required information in these 48 bits. In the second word, the 8 MSbs are ‘0’s. If this second word is executed as an instruction (by itself), it executes as a NOP. The double-word instructions execute in two instruction cycles.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 31-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED) Field Description Wm*Wm Multiplicand and Multiplier Working register pair for Square instructions {W4 * W4,W5 * W5,W6 * W6,W7 * W7} Wm*Wn Multiplicand and Multiplier Working register pair for DSP instructions {W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7} Wn One of 16 Working registers {W0...W15} Wnd One of 16 Destination Working registers {W0...W15} Wns One of 16 Source Working registers {W0...
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 31-2: Base Instr # Assembly Mnemonic 1 ADD 2 3 4 ADDC AND ASR INSTRUCTION SET OVERVIEW Assembly Syntax ADD # of # of Status Flags Words Cycles Affected Description Acc Add Accumulators 1 1 OA,OB,SA, SB ADD f f = f + WREG 1 1 C,DC,N,OV,Z ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC,N,OV,Z ADD Wso,#Slit4,A
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 31-2: Base Instr # Assembly Mnemonic 8 BSW INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax Description # of # of Status Flags Words Cycles Affected BSW.C Ws,Wb Write C bit to Ws 1 1 BSW.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 31-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Instr # Assembly Mnemonic 25 DAW DAW Wn Wn = decimal adjust Wn 1 1 C 26 DEC DEC f f=f–1 1 1 C,DC,N,OV,Z DEC f,WREG WREG = f – 1 1 1 C,DC,N,OV,Z DEC Ws,Wd Wd = Ws – 1 1 1 C,DC,N,OV,Z DEC2 f f=f–2 1 1 C,DC,N,OV,Z DEC2 f,WREG WREG = f – 2 1 1 C,DC,N,OV,Z C,DC,N,OV,Z 27 DEC2 Assembly Syntax # of # of Status Flags Words Cycles Affected Description DEC2 Ws,Wd Wd = Ws – 2 1 1 28 DI
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 31-2: Base Instr # Assembly Mnemonic 46 MOV 47 MOVPAG INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax Description # of # of Status Flags Words Cycles Affected MOV f,Wn Move f to Wn 1 1 None MOV f Move f to f 1 1 None MOV f,WREG Move f to WREG 1 1 None MOV #lit16,Wn Move 16-bit literal to Wn 1 1 None MOV.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 31-2: Base Instr # Assembly Mnemonic 53 NEG 54 55 NOP POP INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax NEG Acc PUSH Negate Accumulator 1 1 OA,OB,OAB, SA,SB,SAB NEG f f=f+1 1 1 C,DC,N,OV,Z NEG f,WREG WREG = f + 1 1 1 C,DC,N,OV,Z NEG Ws,Wd Wd = Ws + 1 1 1 C,DC,N,OV,Z NOP No Operation 1 1 None NOPR No Operation 1 1 None f Pop f from Top-of-Stack (TOS) 1 1 None POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None POP.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 31-2: Base Instr # Assembly Mnemonic 72 SL 73 74 75 76 77 SUB SUBB SUBR SUBBR SWAP INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax Description # of # of Status Flags Words Cycles Affected SL f f = Left Shift f 1 1 C,N,OV,Z SL f,WREG WREG = Left Shift f 1 1 C,N,OV,Z SL Ws,Wd Wd = Left Shift Ws 1 1 C,N,OV,Z SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N,Z SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N,Z SUB Acc Subtract A
dsPIC33EPXXXGM3XX/6XX/7XX NOTES: DS70000689D-page 428 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX 32.
dsPIC33EPXXXGM3XX/6XX/7XX 32.2 MPLAB XC Compilers The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16 and 32-bit MCU and DSC devices. These compilers provide powerful integration capabilities, superior code optimization and ease of use. MPLAB XC Compilers run on Windows, Linux or MAC OS X. For easy source level debugging, the compilers provide debug information that is optimized to the MPLAB X IDE.
dsPIC33EPXXXGM3XX/6XX/7XX 32.6 MPLAB X SIM Software Simulator The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
dsPIC33EPXXXGM3XX/6XX/7XX 32.11 Demonstration/Development Boards, Evaluation Kits and Starter Kits A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification.
dsPIC33EPXXXGM3XX/6XX/7XX 33.0 ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC33EPXXXGM3XX/6XX/7XX electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the dsPIC33EPXXXGM3XX/6XX/7XX family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability.
dsPIC33EPXXXGM3XX/6XX/7XX 33.1 DC Characteristics TABLE 33-1: OPERATING MIPS vs. VOLTAGE VDD Range (in Volts) Characteristic Maximum MIPS Temperature Range (in °C) dsPIC33EPXXXGM3XX/6XX/7XX (1) I-Temp 3.0V to 3.6V -40°C to +85°C 70 E-Temp 3.0V to 3.6V(1) -40°C to +125°C 60 Note 1: Device is functional at VBORMIN < VDD < VDDMIN. Analog modules: ADC, op amp/comparator and comparator voltage reference will have degraded performance. Device functionality is tested but not characterized.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 33-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions (see Note 3): 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param Symbol No. Characteristic Min. Typ.(1) Max. Units 3.0 — 3.6 V Conditions Operating Voltage DC10 VDD Supply Voltage(3) (2) DC12 VDR RAM Data Retention Voltage 1.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 33-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param. Typ.(2) Operating Current (IDD) Max. Units Conditions (1) DC20d 6.0 18.0 mA -40°C DC20a 6.0 18.0 mA +25°C DC20b 6.0 18.0 mA +85°C DC20c 6.0 18.0 mA +125°C DC21d 11.0 20.0 mA -40°C DC21a 11.0 20.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 33-7: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Parameter No. Typ.(2) Max. Units Conditions Idle Current (IIDLE)(1) DC40d 1.5 8.0 mA -40°C DC40a 1.5 8.0 mA +25°C DC40b 1.5 8.0 mA +85°C DC40c 1.5 8.0 mA +125°C DC41d 2.0 12.0 mA -40°C DC41a 2.0 12.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 33-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Parameter No. Typ.(2) Max.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 33-9: DC CHARACTERISTICS: DOZE CURRENT (IDOZE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Doze Ratio Typ.(2) Max. DC73a 20 53 1:2 mA DC73g 8 30 1:128 mA DC70a 19 53 1:2 mA DC70g 8 30 1:128 mA DC71a 20 53 1:2 mA DC71g 10 30 1:128 mA DC72a 25 42 1:2 mA DC72g 12 30 1:128 mA Parameter No.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 33-10: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS DC CHARACTERISTICS Param Symbol No. VIL Characteristic Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Min. Typ. Max. Units Conditions Input Low Voltage DI10 Any I/O Pin and MCLR VSS — 0.2 VDD V DI18 I/O Pins with SDAx, SCLx VSS — 0.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 33-10: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED) DC CHARACTERISTICS Param Symbol No. IIL Characteristic Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Min. Typ. Max.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 33-10: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED) DC CHARACTERISTICS Param Symbol No. IICL Characteristic DI60c 2: 3: 4: 5: 6: 7: 8: Max.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 33-11: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param. Symbol DO10 DO20 VOL VOH DO20A VOH1 Characteristic Min. Typ. Max. Units Conditions Output Low Voltage 4x Sink Driver Pins(1) — — 0.4 V VDD = 3.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 33-13: DC CHARACTERISTICS: PROGRAM MEMORY Standard Operating Conditions: VBOR (min)V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param Symbol No. Characteristic Min Typ(1) Max Units Conditions Program Flash Memory D130 EP Cell Endurance D131 VPR VDD for Read D132b VPEW D134 TRETD D135 10,000 — — VBORMIN — 3.6 VDD for Self-Timed Write 3.0 — 3.
dsPIC33EPXXXGM3XX/6XX/7XX 33.2 AC Characteristics and Timing Parameters This section defines the dsPIC33EPXXXGM3XX/6XX/ 7XX AC characteristics and timing parameters. TABLE 33-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Operating voltage VDD range as described in Section 33.1 “DC Characteristics”.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 33-2: EXTERNAL CLOCK TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 OS20 OS30 OS25 OS30 OS31 OS31 CLKO OS41 OS40 TABLE 33-16: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. OS10 Min. Typ.(1) Max.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 33-17: PLL CLOCK TIMING SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ.(1) Max. Units OS50 FPLLI PLL Voltage Controlled Oscillator (VCO) Input Frequency Range 0.8 — 8.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 33-3: I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) Old Value New Value DO31 DO32 Note: Refer to Figure 33-1 for load conditions. TABLE 33-20: I/O TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ.(1) Max.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 33-5: POWER-ON RESET TIMING CHARACTERISTICS Power-up Timer Disabled – Clock Sources = (FRC, FRCDIVN, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) VDD VPOR Power-up Sequence CPU Starts Fetching Code SY00 (TPU) (Notes 1,2) Power-up Timer Disabled – Clock Sources = (HS, HSPLL, XT and XTPLL) VDD VPOR Power-up Sequence CPU Starts Fetching Code SY00 (TPU) (Notes 1,2) SY10 (TOST) Power-up Timer Enabled – Clock Sources = (FRC, FRCDIVN, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) VDD VPOR
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 33-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param No. Min. Typ.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 33-6: TIMER1-TIMER5 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx11 Tx10 Tx15 OS60 Tx20 TMRx Note: Refer to Figure 33-1 for load conditions. TABLE 33-22: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. TA10 Symbol TTXH Characteristic(2) Min. Typ. Max.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 33-23: TIMER2 AND TIMER4 (TYPE B TIMER) EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic(1) Min. Typ. Max.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 33-7: INPUT CAPTURE x (ICx) TIMING CHARACTERISTICS ICx IC10 IC11 IC15 Note: Refer to Figure 33-1 for load conditions. TABLE 33-25: INPUT CAPTURE x (ICx) TIMING REQUIREMENTS AC CHARACTERISTICS Param. Symbol No. Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Characteristics(1) Min. Max. Units Conditions IC10 TCCL ICx Input Low Time Greater of: 12.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 33-8: OUTPUT COMPARE x (OCx) TIMING CHARACTERISTICS OCx (Output Compare or PWM Mode) OC11 OC10 Note: Refer to Figure 33-1 for load conditions. TABLE 33-26: OUTPUT COMPARE x (OCx) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param Symbol No. Characteristic(1) Min. Typ. Max.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 33-10: HIGH-SPEED PWMx MODULE FAULT TIMING CHARACTERISTICS MP30 Fault Input (active-low) MP20 PWMx FIGURE 33-11: HIGH-SPEED PWMx MODULE TIMING CHARACTERISTICS MP11 MP10 PWMx Note: Refer to Figure 33-1 for load conditions. TABLE 33-28: HIGH-SPEED PWMx MODULE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 33-12: TIMERQ (QEIx MODULE) EXTERNAL CLOCK TIMING CHARACTERISTICS QEBx TQ11 TQ10 TQ15 TQ20 POSCNT TABLE 33-29: QEIx MODULE EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic(1) Min. Typ. Max.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 33-13: QEAx/QEBx INPUT CHARACTERISTICS TQ36 QEAx (input) TQ31 TQ30 TQ35 QEBx (input) TQ41 TQ40 TQ30 TQ31 TQ35 QEBx Internal TABLE 33-30: QUADRATURE DECODER TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic(1) Typ.(2) Max.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 33-14: QEIx MODULE INDEX PULSE TIMING CHARACTERISTICS QEAx (input) QEBx (input) Ungated Index TQ50 TQ51 Index Internal TQ55 Position Counter Reset TABLE 33-31: QEIx INDEX PULSE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param Symbol No. Characteristic(1) Min. Max.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 33-32: SPI2 AND SPI3 MAXIMUM DATA/CLOCK RATE SUMMARY Standard Operating Conditions: 3.0V to 3.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 33-16: SPI2 AND SPI3 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 1) TIMING CHARACTERISTICS SP36 SCKx (CKP = 0) SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 SDOx Bit 14 - - - - - -1 MSb LSb SP30, SP31 Note: Refer to Figure 33-1 for load conditions. TABLE 33-33: SPI2 AND SPI3 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 33-17: SPI2 AND SPI3 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING CHARACTERISTICS SP36 SCKx (CKP = 0) SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 Bit 14 - - - - - -1 MSb SDOx SP30, SP31 SP40 SDIx LSb MSb In LSb In Bit 14 - - - -1 SP41 Note: Refer to Figure 33-1 for load conditions. TABLE 33-34: SPI2 AND SPI3 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 33-18: SPI2 AND SPI3 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING CHARACTERISTICS SCKx (CKP = 0) SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 SP36 Bit 14 - - - - - -1 MSb SDOx SP30, SP31 SDIx MSb In LSb SP30, SP31 LSb In Bit 14 - - - -1 SP40 SP41 Note: Refer to Figure 33-1 for load conditions. TABLE 33-35: SPI2 AND SPI3 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 33-19: SPI2 AND SPI3 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS SP60 SSx SP52 SP50 SCKx (CKP = 0) SP70 SP73 SCKx (CKP = 1) SP36 SP35 MSb SDOx Bit 14 - - - - - -1 SP72 MSb In Bit 14 - - - -1 SP73 LSb SP30, SP31 SDIx SP72 SP51 LSb In SP41 SP40 Note: Refer to Figure 33-1 for load conditions. 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 33-36: SPI2 AND SPI3 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param. Symbol Characteristic(1) Min. Typ.(2) Max.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 33-20: SPI2 AND SPI3 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS SP60 SSx SP52 SP50 SCKx (CKP = 0) SP70 SP73 SCKx (CKP = 1) SP72 SP36 SP35 SP72 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 SDIx MSb In Bit 14 - - - -1 SP73 SP51 LSb In SP41 SP40 Note: Refer to Figure 33-1 for load conditions. 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 33-37: SPI2 AND SPI3 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param. Symbol Characteristic(1) Min. Typ.(2) Max.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 33-21: SPI2 AND SPI3 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS SSX SP52 SP50 SCKX (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 SP36 SDOX MSb Bit 14 - - - - - -1 LSb SP51 SP30, SP31 SDIX MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure 33-1 for load conditions. 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 33-38: SPI2 AND SPI3 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param. Symbol Characteristic(1) Min. Typ.(2) Max.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 33-22: SPI2 AND SPI3 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS SSX SP52 SP50 SCKX (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 SP36 MSb SDOX Bit 14 - - - - - -1 LSb SP51 SP30, SP31 SDIX MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure 33-1 for load conditions. 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 33-39: SPI2 AND SPI3 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param. Symbol Characteristic(1) Min. Typ.(2) Max.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 33-40: SPI1 MAXIMUM DATA/CLOCK RATE SUMMARY Standard Operating Conditions: 3.0V to 3.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 33-24: SPI1 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 1) TIMING CHARACTERISTICS SP36 SCK1 (CKP = 0) SP10 SP21 SP20 SP20 SP21 SCK1 (CKP = 1) SP35 Bit 14 - - - - - -1 MSb SDO1 LSb SP30, SP31 Note: Refer to Figure 33-1 for load conditions. TABLE 33-41: SPI1 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 33-25: SPI1 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING CHARACTERISTICS SP36 SCK1 (CKP = 0) SP10 SP21 SP20 SP20 SP21 SCK1 (CKP = 1) SP35 Bit 14 - - - - - -1 MSb SDO1 SP30, SP31 SP40 SDI1 LSb MSb In LSb In Bit 14 - - - -1 SP41 Note: Refer to Figure 33-1 for load conditions. TABLE 33-42: SPI1 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 33-26: SPI1 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING CHARACTERISTICS SCK1 (CKP = 0) SP10 SP21 SP20 SP20 SP21 SCK1 (CKP = 1) SP35 SP36 MSb SDO1 Bit 14 - - - - - -1 SP30, SP31 SD1 MSb In LSb SP30, SP31 LSb In Bit 14 - - - -1 SP40 SP41 Note: Refer to Figure 33-1 for load conditions. TABLE 33-43: SPI1 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 33-27: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS SP60 SS1 SP52 SP50 SCK1 (CKP = 0) SP70 SP73 SCK1 (CKP = 1) SP72 SP36 SP35 SP72 SDO1 MSb Bit 14 - - - - - -1 LSb SP30, SP31 SDI1 MSb In Bit 14 - - - -1 SP73 SP51 LSb In SP41 SP40 Note: Refer to Figure 33-1 for load conditions. 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 33-44: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param. Symbol Characteristic(1) Min. Typ.(2) Max.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 33-28: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS SP60 SS1 SP52 SP50 SCK1 (CKP = 0) SP70 SP73 SCK1 (CKP = 1) SP72 SP36 SP35 SP72 SDO1 MSb Bit 14 - - - - - -1 LSb SP30, SP31 SDI1 MSb In Bit 14 - - - -1 SP73 SP51 LSb In SP41 SP40 Note: Refer to Figure 33-1 for load conditions. 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 33-45: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param. Symbol Characteristic(1) Min. Typ.(2) Max.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 33-29: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS SS1 SP52 SP50 SCK1 (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCK1 (CKP = 1) SP35 SP36 MSb SDO1 Bit 14 - - - - - -1 LSb SP51 SP30, SP31 SDI1 MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure 33-1 for load conditions. 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 33-46: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param. Symbol Characteristic(1) Min. Typ.(2) Max.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 33-30: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS SS1 SP52 SP50 SCK1 (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCK1 (CKP = 1) SP35 SP36 SDO1 MSb Bit 14 - - - - - -1 LSb SP51 SP30, SP31 SDI1 MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure 33-1 for load conditions. 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 33-47: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param. Symbol Characteristic(1) Min. Typ.(2) Max.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 33-31: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM34 IM30 IM33 SDAx Stop Condition Start Condition Note: Refer to Figure 33-1 for load conditions. FIGURE 33-32: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM21 IM11 IM10 SCLx IM26 IM11 IM10 IM25 IM33 SDAx In IM40 IM40 IM45 SDAx Out Note: Refer to Figure 33-1 for load conditions. 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 33-48: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param Symbol No. IM10 IM11 IM20 IM21 IM25 IM26 IM30 IM31 IM33 IM34 IM40 IM45 IM50 IM51 Note 1: 2: 3: 4: Characteristic(4) Min.(1) Max.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 33-33: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS34 IS31 IS30 IS33 SDAx Stop Condition Start Condition FIGURE 33-34: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS21 IS11 IS10 SCLx IS30 IS25 IS31 IS26 IS33 SDAx In IS40 IS40 IS45 SDAx Out 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 33-49: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param. Symbol No. Characteristic(3) IS10 TLO:SCL Clock Low Time IS11 THI:SCL IS20 IS21 IS25 IS26 IS30 IS31 IS33 IS34 IS40 IS45 IS50 IS51 Note Clock High Time Min. Max.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 33-35: CANx MODULE I/O TIMING CHARACTERISTICS CxTX Pin (output) New Value Old Value CA10 CA11 CxRX Pin (input) CA20 TABLE 33-50: CANx MODULE I/O TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Characteristic(1) Symbol CA10 Min. Typ.(2) Max.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 33-52: OP AMP/COMPARATOR SPECIFICATIONS Standard Operating Conditions (see Note 3): 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param No. Min. Typ.(1) Max.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 33-53: OP AMP/COMPARATOR VOLTAGE REFERENCE SETTLING TIME SPECIFICATIONS Standard Operating Conditions (see Note 2): 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param. VR310 Note 1: 2: Symbol TSET Characteristic Min. Typ. Max.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 33-55: CTMU CURRENT SOURCE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param No. Characteristic(1) Symbol Min. Typ. Max. Units nA Conditions CTMU Current Source CTMUI1 IOUT1 Base Range 280 550 830 CTMUI2 IOUT2 10x Range 2.8 5.5 8.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 33-56: ADCx MODULE SPECIFICATIONS AC CHARACTERISTICS Param Symbol No. Characteristic Standard Operating Conditions (see Note 1): 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Min. Typ. Max. Units Conditions Device Supply AD01 AVDD Module VDD Supply Greater of: VDD – 0.3 or 3.0 — Lesser of: VDD + 0.3 or 3.6 V AD02 AVSS Module VSS Supply VSS – 0.3 — VSS + 0.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 33-57: ADCx MODULE SPECIFICATIONS (12-BIT MODE) Standard Operating Conditions (see Note 1): 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ. Max.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 33-58: ADCx MODULE SPECIFICATIONS (10-BIT MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)(1) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ. Max.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 33-38: ADC1 CONVERSION (12-BIT MODE) TIMING CHARACTERISTICS (ASAM = 0, SSRC<2:0> = 000, SSRCG = 0) AD50 ADCLK Instruction Set SAMP Execution Clear SAMP SAMP AD61 AD60 TSAMP AD55 DONE AD1IF 1 2 3 4 5 6 7 8 9 1 – Software sets AD1CON1. SAMP to start sampling. 5 – Convert bit 11. 2 – Sampling starts after discharge period. TSAMP is described in “Analog-to-Digital Converter (ADC)” (DS70621) of the “dsPIC33/PIC24 Family Reference Manual”.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 33-59: ADCx CONVERSION (12-BIT MODE) TIMING REQUIREMENTS Standard Operating Conditions (see Note 2): 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param Symbol No. Characteristic Min. Typ.(4) Max.
dsPIC33EPXXXGM3XX/6XX/7XX FIGURE 33-39: ADC1 CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000, SSRCG = 0) AD50 ADCLK Instruction Set SAMP Execution Clear SAMP SAMP AD61 AD60 AD55 TSAMP AD55 DONE AD1IF 1 2 3 4 5 6 7 8 5 6 7 1 – Software sets AD1CON1. SAMP to start sampling. 5 – Convert bit 9. 2 – Sampling starts after discharge period.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 33-60: ADCx CONVERSION (10-BIT MODE) TIMING REQUIREMENTS Standard Operating Conditions (see Note 1): 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param Symbol No. Characteristic Min. Typ.(4) Max.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 33-61: DMA MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Param No. DM1 Note 1: 2: Characteristic DMA Byte/Word Transfer Latency Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Min. Typ.(1) Max. Units 1 TCY(2) — — ns Conditions These parameters are characterized, but not tested in manufacturing.
dsPIC33EPXXXGM3XX/6XX/7XX 34.0 HIGH-TEMPERATURE ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC33EPXXXGM3XX/6XX/7XX electrical characteristics for devices operating in an ambient temperature range of -40°C to +150°C. The specifications between -40°C to +150°C are identical to those shown in Section 33.0 “Electrical Characteristics” for operation between -40°C to +125°C, with the exception of the parameters listed in this section.
dsPIC33EPXXXGM3XX/6XX/7XX 34.1 High-Temperature DC Characteristics TABLE 34-1: OPERATING MIPS VS. VOLTAGE VDD Range (in Volts) Characteristic HDC5 3.0 to Max MIPS Temperature Range (in °C) dsPIC33EPXXXGM3XX/6XX/7XX -40°C to +150°C 40 3.6V(1) Device is functional at VBORMIN < VDD < VDDMIN. Analog modules, such as the ADC, may have degraded performance. Device functionality is tested but not characterized.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 34-5: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +150°C DC CHARACTERISTICS Parameter No. HDC40e Typical Max Units Conditions 3.6 8 mA +150°C 3.3V 10 MIPS HDC42e 5 15 mA +150°C 3.3V 20 MIPS HDC44e 10 20 mA +150°C 3.3V 40 MIPS TABLE 34-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 3.0V to 3.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 34-8: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +150°C DC CHARACTERISTICS Param. HDO10 HDO20 Symbol VOL VOH HDO20A VOH1 Characteristic Min. Typ. Max. Units Output Low Voltage 4x Sink Driver Pins(2) — — 0.4 V IOL 5 mA, VDD = 3.3V (Note 1) Output Low Voltage 8x Sink Driver Pins(3) — — 0.4 V IOL 8 mA, VDD = 3.
dsPIC33EPXXXGM3XX/6XX/7XX 34.2 AC Characteristics and Timing Parameters The information contained in this section defines dsPIC33EPXXXGM3XX/6XX/7XX AC characteristics and timing parameters for high-temperature devices. However, all AC timing specifications in this section are the same as those in Section 33.2 “AC Characteristics and Timing Parameters”, with the exception of the parameters listed in this section. Parameters in this section begin with an H, which denotes High temperature.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 34-11: PLL CLOCK TIMING SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +150°C AC CHARACTERISTICS Param No. Symbol Characteristic CLKO Stability (Jitter)(1) Min Typ Max Units -5 0.5 5 % Conditions Measured over 100 ms period HOS53 DCLK Note 1: These parameters are characterized by similarity, but are not tested in manufacturing.
dsPIC33EPXXXGM3XX/6XX/7XX TABLE 34-14: ADCx MODULE SPECIFICATIONS (12-BIT MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +150°C AC CHARACTERISTICS Param No. Symbol Characteristic Min Typ Max Units Conditions ADC Accuracy (12-Bit Mode)(1) HAD20a Nr Resolution(3) HAD21a INL Integral Nonlinearity -6 — 6 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.
dsPIC33EPXXXGM3XX/6XX/7XX NOTES: DS70000689D-page 506 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX 35.0 PACKAGING INFORMATION 35.1 Package Marking Information 44-Lead TQFP (10x10x1 mm) XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN dsPIC33EP 512GM604 -I/ML e3 1410017 44-Lead QFN (8x8x0.9 mm) XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX YYWWNNN Note: Example dsPIC33EP 512GM604 -I/MLe3 1410017 64-Lead QFN (9x9x0.9 mm) Legend: XX...
dsPIC33EPXXXGM3XX/6XX/7XX 35.1 Package Marking Information (Continued) 64-Lead TQFP (10x10x1 mm) XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 100-Lead TQFP (12x12x1 mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 100-Lead TQFP (14x14x1 mm) XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 121-Lead TFBGA (10x10x1.
dsPIC33EPXXXGM3XX/6XX/7XX 35.2 Package Details /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 ± [ [ PP %RG\ PP >74)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D1 E e E1 N b NOTE 1 1 2 3 NOTE 2 α A φ c β A2 A1 L L1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI /HDGV 0,//,0(7(56 0,1 1 120 0$; /HDG 3LWFK H 2YHUDOO +HLJKW $ ± %6& ± 0ROGHG 3DFNDJH 7KLFNQHVV $ 6WDQGRI
dsPIC33EPXXXGM3XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70000689D-page 510 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX DS70000689D-page 512 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70000689D-page 514 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70000689D-page 516 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX 64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 D1/2 D NOTE 2 A B E1/2 E1 A E A SEE DETAIL 1 N 4X N/4 TIPS 0.20 C A-B D 1 3 2 4X NOTE 1 0.20 H A-B D TOP VIEW A2 A 0.05 C SEATING PLANE 0.08 C 64 X b 0.
dsPIC33EPXXXGM3XX/6XX/7XX 64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP] For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
dsPIC33EPXXXGM3XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 ± [ [ PP %RG\ PP >74)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D1 e E E1 N b NOTE 1 1 23 NOTE 2 α c A φ L β A1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI /HDGV A2 L1 0,//,0(7(56 0,1 1 120 0$; /HDG 3LWFK H 2YHUDOO +HLJKW $ ± %6& ± 0ROGHG 3DFNDJH 7KLFNQHVV $ 6WDQGRII $ ±
dsPIC33EPXXXGM3XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 3) ± [ [ PP %RG\ PP >74)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D1 e E1 E b N α NOTE 1 1 23 A NOTE 2 φ c β A2 A1 L L1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI /HDGV 0,//,0(7(56 0,1 1 120 0$; /HDG 3LWFK H 2YHUDOO +HLJKW $ ± %6& ± 0ROGHG 3DFNDJH 7KLFNQHVV $ 6WDQGRII $ ±
dsPIC33EPXXXGM3XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX 121-Ball Plastic Thin Profile Fine Pitch Ball Grid Array (BG) 10x10x1.10 mm Body [TFBGA] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B NOTE 1 E (DATUM B) (DATUM A) 2X 0.10 C 2X 0.
dsPIC33EPXXXGM3XX/6XX/7XX 121-Ball Plastic Thin Profile Fine Pitch Ball Grid Array (BG) 10x10x1.10 mm Body [TFBGA] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C 0.10 C DETAIL A NX Øb 0.15 0.08 C A B C DETAIL B Number of Contacts Contact Pitch Overall Height Ball Height Overall Width Array Width Overall Length Array Length Contact Diameter Units Dimension Limits N e A A1 E E1 D D1 b MIN 1.00 0.25 0.
dsPIC33EPXXXGM3XX/6XX/7XX DS70000689D-page 526 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX APPENDIX A: REVISION HISTORY Revision A (February 2013) This is the initial released version of this document. Revision B (June 2013) Changes to Section 5.0 “Flash Program Memory”, Register 5-1. Changes to Section 6.0 “Resets”, Figure 6-1. Changes to Section 26.0 “Op Amp/Comparator Module”, Register 26-2. Updates to most of the tables in Section 33.0 “Electrical Characteristics”. Minor text edits throughout the document. Revision C (September 2013) Changes to Figure 23-1.
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dsPIC33EPXXXGM3XX/6XX/7XX INDEX Timer2 and Timer4 (Type B) External Clock Requirements ................................................... 452 Timer3 and Timer5 (Type C) External Clock Requirements ................................................... 452 UARTx I/O Requirements......................................... 487 A Absolute Maximum Ratings .............................................. 433 AC Characteristics ....................................................
dsPIC33EPXXXGM3XX/6XX/7XX PMP Pinout and Connections to External Devices ............................................... 395 Programmer’s Model................................................... 30 PTG Module .............................................................. 350 QEIx Module ............................................................. 258 Recommended Minimum Connection ......................... 22 Remappable Input for U1RX ..................................... 166 Reset System..................
dsPIC33EPXXXGM3XX/6XX/7XX F Flash Program Memory .................................................... 103 Control Registers ...................................................... 104 Operations ................................................................ 104 RTSP Operation........................................................ 104 Table Instructions...................................................... 103 Flexible Configuration .......................................................
dsPIC33EPXXXGM3XX/6XX/7XX Program Address Space ..................................................... 37 Memory Map for dsPIC33EP128GM3XX/6XX/7XX Devices ......... 37 Memory Map for dsPIC33EP256GM3XX/6XX/7XX Devices ......... 38 Memory Map for dsPIC33EP512GM3XX/6XX/7XX Devices ......... 39 Program Memory Organization................................................................ 40 Reset Vector ............................................................... 40 Program Space Address Construction............
dsPIC33EPXXXGM3XX/6XX/7XX AUXCONx (PWMx Auxiliary Control)........................ 254 CHOP (PWMx Chop Clock Generator)..................... 241 CLKDIV (Clock Divisor)............................................. 148 CM4CON (Op Amp/Comparator 4 Control) .............. 373 CMSTAT (Op Amp/Comparator Status) ................... 370 CMxCON (Op Amp/Comparator x Control, x = 1, 2, 3 or 5) .................................... 371 CMxFLTR (Comparator x Filter Control)...................
dsPIC33EPXXXGM3XX/6XX/7XX PMCON (Parallel Master Port Control) ..................... 396 PMD1 (Peripheral Module Disable Control 1) ........... 156 PMD2 (Peripheral Module Disable Control 2) ........... 158 PMD3 (Peripheral Module Disable Control 3) ........... 159 PMD4 (Peripheral Module Disable Control 4) ........... 161 PMD6 (Peripheral Module Disable Control 6) ........... 161 PMD7 (Peripheral Module Disable Control 7) ........... 162 PMMODE (Parallel Master Port Mode) .....................
dsPIC33EPXXXGM3XX/6XX/7XX Resets ............................................................................... 111 Brown-out Reset (BOR) ............................................ 111 Configuration Mismatch Reset (CM)......................... 111 Illegal Condition Reset (IOPUWR)............................ 111 Illegal Address Mode ........................................ 111 Illegal Opcode ................................................... 111 Security ..................................................
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dsPIC33EPXXXGM3XX/6XX/7XX THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
dsPIC33EPXXXGM3XX/6XX/7XX NOTES: DS70000689D-page 538 2013-2014 Microchip Technology Inc.
dsPIC33EPXXXGM3XX/6XX/7XX PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Example: dsPIC 33 EP 512 GM7 10 T - I / PT XXX Microchip Trademark Architecture dsPIC33EP512GM710-I/PT: dsPIC33, Enhanced Performance, 512-Kbyte program memory, 100-pin, Industrial temperature, TQFP package.
dsPIC33EPXXXGM3XX/6XX/7XX NOTES: DS70000689D-page 540 2013-2014 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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