Datasheet

 2018 Microchip Technology Inc. Data Sheet Complete DS40002059A-page 99
ATxmega32E5/16E5/8E5
Notes: 1. Required only for f
SCL
> 100kHz.
2. C
b
= Capacitance of one bus line in pF.
3. f
PER
= Peripheral clock frequency.
t
LOW
Low period of SCL Clock
f
SCL
≤ 100kHz 4.7
µs
f
SCL
≤ 400kHz 1.3
f
SCL
≤ 1MHz 0.5
t
HIGH
High period of SCL Clock
f
SCL
≤ 100kHz 4
f
SCL
≤ 400kHz 0.6
f
SCL
≤ 1MHz 0.26
t
SU;STA
Set-up time for a repeated START
condition
f
SCL
≤ 100kHz 4.7
f
SCL
≤ 400kHz 0.6
f
SCL
≤ 1MHz 0.26
t
HD;DAT
Data hold time
f
SCL
≤ 100kHz 0 3.45
f
SCL
≤ 400kHz 0 0.9
f
SCL
≤ 1MHz 0 0.45
t
SU;DAT
Data setup time
f
SCL
≤ 100kHz 250
nsf
SCL
≤ 400kHz 100
f
SCL
≤ 1MHz 50
t
SU;STO
Setup time for STOP condition
f
SCL
≤ 100kHz 4
µs
f
SCL
≤ 400kHz 0.6
f
SCL
≤ 1MHz 0.26
t
BUF
Bus free time between a STOP
and START condition
f
SCL
≤ 100kHz 4.7
f
SCL
≤ 400kHz 1.3
f
SCL
≤ 1MHz 0.5
Symbol Parameter Condition Min. Typ. Max. Units