Datasheet

 2018 Microchip Technology Inc. Data Sheet Complete DS40002059A-page 50
ATxmega32E5/16E5/8E5
23. SPI – Serial Peripheral Interface
23.1 Features
 One SPI peripheral
 Full-duplex, three-wire synchronous data transfer
 Master or slave operation
 lsb first or msb first data transfer
 Eight programmable bit rates
 Interrupt flag at the end of transmission
 Write collision flag to indicate data collision
 Wake up from idle sleep mode
 Double speed master mode
23.2 Overview
The Serial Peripheral Interface (SPI) is a high-speed, full duplex, synchronous data transfer interface using three or four
pins. It allows fast communication between an AVR XMEGA device and peripheral devices or between several
microcontrollers.
A device connected to the bus must act as a master or slave. The master initiates and controls all data transactions. The
interconnection between master and slave devices with SPI is shown in Figure 23-1. The system consists of two shift reg-
isters and a clock generator. The SPI master initiates the communication by pulling the slave select (SS) signal low for the
desired slave. Master and slave prepare the data to be sent in their respective shift registers, and the master generates the
required clock pulses on the SCK line to interchange data. Data are always shifted from master to slave on the master out-
put, slave input (MOSI) line, and from slave to master on the master input, slave output (MISO) line. After each data packet,
the master can synchronize the slave by pulling the SS
line high.
Figure 23-1. SPI Master-slave Interconnection
By default, the SPI module is single buffered and transmit direction and double buffered in the receive direction. A byte writ-
ten to the transmit data register will be copied to the shift register when a full character has been received. When receiving
data, a received character must be read from the transmit data register before the third character has been completely
shifted in to avoid losing data. Optionally, buffer modes can be enabled. When used, one buffer is available for transmitter
and a double buffer for reception.
PORTC has one SPI. Notation of this is SPIC.
8-bit Shift Register
msb
Transmit Data Register
(DATA)
Receive Buffer Register
Receive Data Register
(DATA)
MOSI lsb
MISO
SCK
SS
SLAVE
8-bit Shift Register
msb
Transmit Data Register
(DATA)
Receive Buffer Register
Receive Data Register
(DATA)
MOSI
lsb MISO
SCK
SS
MASTER
SPI CLOCK
GENERATOR