Datasheet

29
XMEGA A4U [DATASHEET]
Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014
14. Interrupts and Programmable Multilevel Interrupt Controller
14.1 Features
z Short and predictable interrupt response time
z Separate interrupt configuration and vector address for each interrupt
z Programmable multilevel interrupt controller
z Interrupt prioritizing according to level and vector address
z Three selectable interrupt levels for all interrupts: low, medium and high
z Selectable, round-robin priority scheme within low-level interrupts
z Non-maskable interrupts for critical functions
z Interrupt vectors optionally placed in the application section or the boot loader section
14.2 Overview
Interrupts signal a change of state in peripherals, and this can be used to alter program execution. Peripherals can
have one or more interrupts, and all are individually enabled and configured. When an interrupt is enabled and
configured, it will generate an interrupt request when the interrupt condition is present. The programmable multilevel
interrupt controller (PMIC) controls the handling and prioritizing of interrupt requests. When an interrupt request is
acknowledged by the PMIC, the program counter is set to point to the interrupt vector, and the interrupt handler can
be executed.
All peripherals can select between three different priority levels for their interrupts: low, medium, and high. Interrupts
are prioritized according to their level and their interrupt vector address. Medium-level interrupts will interrupt low-level
interrupt handlers. High-level interrupts will interrupt both medium- and low-level interrupt handlers. Within each level,
the interrupt priority is decided from the interrupt vector address, where the lowest interrupt vector address has the
highest interrupt priority. Low-level interrupts have an optional round-robin scheduling scheme to ensure that all
interrupts are serviced within a certain amount of time.
Non-maskable interrupts (NMI) are also supported, and can be used for system critical functions.
14.3 Interrupt vectors
The interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for specific interrupts
in each peripheral. The base addresses for the Atmel AVR XMEGA A4U devices are shown in Table 14-1 on page 30.
Offset addresses for each interrupt available in the peripheral are described for each peripheral in the XMEGA AU
manual. For peripherals or modules that have only one interrupt, the interrupt vector is shown in Table 14-1 on page
30. The program address is the word address.