8/16-bit Atmel XMEGA Microcontroller ATxmega128A4U / ATxmega64A4U / ATxmega32A4U / ATxmega16A4U Features z High-performance, low-power Atmel® AVR® XMEGA® 8/16-bit Microcontroller z Nonvolatile program and data memories 16K - 128KB of in-system self-programmable flash 4K - 8KB boot section 1K - 2KB EEPROM 2K - 8KB internal SRAM Peripheral Features z Four-channel DMA controller z Eight-channel event system z Five 16-bit timer/counters z Three timer/counters with 4 output compare or input capture channels z
1.
Ordering code Flash (bytes) EEPROM (bytes) SRAM (bytes) ATxmega128A4U-AN 128K + 8K 2K 8K ATxmega128A4U-ANR(4) 128K + 8K 2K 8K ATxmega64A4U-AN 64K + 4K 2K 4K ATxmega64A4U-ANR(4) 64K + 4K 2K 4K ATxmega32A4U-AN 32K + 4K 1K 4K ATxmega32A4U-ANR(4) 32K + 4K 1K 4K ATxmega16A4U-AN 16K + 4K 1K 2K ATxmega16A4U-ANR(4) 16K + 4K 1K 2K ATxmega128A4U-M7 128K + 8K 2K 8K ATxmega128A4U-M7R(4) 128K + 8K 2K 8K ATxmega64A4U-M7 64K + 4K 2K 4K ATxmega64A4U-M7R(4) 64K + 4K 2K 4K
2. Pinout/Block Diagram Figure 2-1.
Figure 2-2. BGA pinout Top view 1 2 3 4 5 Bottom view 6 7 7 6 5 4 3 2 1 A A B B C C D D E E F F G G Table 2-1.
3. Overview The Atmel AVR XMEGA is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the AVR XMEGA devices achieve CPU throughput approaching one million instructions per second (MIPS) per megahertz, allowing the system designer to optimize power consumption versus processing speed. The AVR CPU combines a rich instruction set with 32 general purpose working registers.
3.1 Block Diagram Figure 3-1. XMEGA A4U Block Diagram PR[0..1] Digital function Programming, debug, test Analog function Oscillator/Crystal/Clock XTAL1/ TOSC1 General Purpose I/O XTAL2/ TOSC2 Oscillator Circuits/ Clock Generation PORT R (2) Real Time Counter DATA BUS PA[0..
4. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 4.1 Recommended reading z Atmel AVR XMEGA AU manual z XMEGA application notes This device data sheet only contains part specific information with a short description of each peripheral and module. The XMEGA AU manual describes the modules and peripherals in depth.
6. AVR CPU 6.1 Features z 8/16-bit, high-performance Atmel AVR RISC CPU z z 142 instructions Hardware multiplier z 32x8-bit registers directly connected to the ALU z Stack in RAM z Stack pointer accessible in I/O memory space z Direct addressing of up to 16MB of program memory and 16MB of data memory z True 16/24-bit access to 16/24-bit I/O registers z Efficient support for 8-, 16-, and 32-bit arithmetic z Configuration change protection of system-critical features 6.
Figure 6-1. Block diagram of the AVR CPU architecture. The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register is updated to reflect information about the result of the operation. The ALU is directly connected to the fast-access register file.
purpose registers. In a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed and the result is stored in the register file. After an arithmetic or logic operation, the status register is updated to reflect information about the result of the operation. ALU operations are divided into three main categories – arithmetic, logical, and bit functions.
During interrupts or subroutine calls, the return address is automatically pushed on the stack. The return address can be two or three bytes, depending on program memory size of the device. For devices with 128KB or less of program memory, the return address is two bytes, and hence the stack pointer is decremented/incremented by two. For devices with more than 128KB of program memory, the return address is three bytes, and hence the SP is decremented/incremented by three.
7. Memories 7.
7.3 Flash Program Memory The Atmel AVR XMEGA devices contain on-chip, in-system reprogrammable flash memory for program storage. The flash memory can be accessed for read and write from an external programmer through the PDI or from application software running in the device. All AVR CPU instructions are 16 or 32 bits wide, and each flash location is 16 bits wide. The flash memory is organized in two main sections, the application section and the boot loader section.
7.3.4 Production Signature Row The production signature row is a separate memory section for factory programmed data. It contains calibration data for functions such as oscillators and analog modules. Some of the calibration values will be automatically loaded to the corresponding module or peripheral unit during reset. Other values must be loaded from the signature row and written to the corresponding peripheral registers from software.
Figure 7-1. Data memory map (Hexadecimal address).
7.8 Data Memory and Bus Arbitration Since the data memory is organized as four separate sets of memories, the different bus masters (CPU, DMA controller read and DMA controller write, etc.) can access different memory sections at the same time. 7.9 Memory Timing Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes one cycle, and a read from SRAM takes two cycles. For burst read (DMA), new data are available every cycle.
Table 7-4. Number of bytes and pages in the EEPROM.
8. DMAC – Direct Memory Access Controller 8.
9. Event System 9.
10. System Clock and Clock options 10.1 Features z Fast start-up time z Safe run-time clock switching z Internal oscillators: 32MHz run-time calibrated and tuneable oscillator 2MHz run-time calibrated oscillator z 32.768kHz calibrated oscillator z 32kHz ultra low power (ULP) oscillator with 1kHz output z z z External clock options 0.4MHz - 16MHz crystal oscillator 32.
Figure 10-1. The clock system, clock sources and clock distribution. Real Time Counter RAM Peripherals AVR CPU Non-Volatile Memory clkPER clkCPU clkPER2 clkPER4 USB clkUSB Brown-out Detector System Clock Prescalers Watchdog Timer Prescaler clkSYS clkRTC System Clock Multiplexer (SCLKSEL) RTCSRC USBSRC DIV32 DIV32 DIV32 PLL PLLSRC DIV4 XOSCSEL 32 kHz Int. ULP 32.768 kHz Int. OSC 32.768 kHz TOSC 32 MHz Int. Osc 2 MHz Int. Osc XTAL2 XTAL1 TOSC2 TOSC1 10.3 0.
a 1kHz output. The oscillator is automatically enabled/disabled when it is used as clock source for any part of the device. This oscillator can be selected as the clock source for the RTC. 10.3.2 32.768kHz Calibrated Internal Oscillator This oscillator provides an approximate 32.768kHz clock. It is calibrated during production to provide a default frequency close to its nominal frequency. The calibration register can also be written from software for run-time calibration of the oscillator frequency.
11. Power Management and Sleep Modes 11.1 Features z Power management for adjusting power consumption and functions z Five sleep modes Idle Power down z Power save z Standby z Extended standby z z z Power reduction register to disable clock and turn off unused peripherals in active and idle modes 11.2 Overview Various sleep modes and clock gating are provided in order to tailor power consumption to application requirements.
11.3.3 Power-save Mode Power-save mode is identical to power down, with one exception. If the real-time counter (RTC) is enabled, it will keep running during sleep, and the device can also wake up from either an RTC overflow or compare match interrupt. 11.3.4 Standby Mode Standby mode is identical to power down, with the exception that the enabled system clock sources are kept running while the CPU, peripheral, and RTC clocks are stopped. This reduces the wake-up time. 11.3.
12. System Control and Reset 12.1 Features z Reset the microcontroller and set it to initial state when a reset source goes active z Multiple reset sources that cover different situations z z z z z z Power-on reset External reset Watchdog reset Brownout reset PDI reset Software reset z Asynchronous operation z No running system clock in the device is required for reset z Reset status register for reading the reset source from the application code 12.
12.4.2 Brownout Detection The on-chip brownout detection (BOD) circuit monitors the VCC level during operation by comparing it to a fixed, programmable level that is selected by the BODLEVEL fuses. If disabled, BOD is forced on at the lowest level during chip erase and when the PDI is enabled. 12.4.3 External Reset The external reset circuit is connected to the external RESET pin.
13. WDT – Watchdog Timer 13.1 Features z Issues a device reset if the timer is not reset before its timeout period z Asynchronous operation from dedicated oscillator z 1kHz output of the 32kHz ultra low power oscillator z 11 selectable timeout periods, from 8ms to 8s z Two operation modes: z z Normal mode Window mode z Configuration lock to prevent unwanted changes 13.2 Overview The watchdog timer (WDT) is a system function for monitoring correct program operation.
14. Interrupts and Programmable Multilevel Interrupt Controller 14.
Table 14-1.
15. I/O Ports 15.
15.3.1 Push-pull Figure 15-1. I/O configuration - Totem-pole. DIRn OUTn Pn INn 15.3.2 Pull-down Figure 15-2. I/O configuration - Totem-pole with pull-down (on input). DIRn OUTn Pn INn 15.3.3 Pull-up Figure 15-3. I/O configuration - Totem-pole with pull-up (on input). DIRn OUTn Pn INn 15.3.4 Bus-keeper The bus-keeper’s weak output produces the same logical level as the last output level. It acts as a pull-up if the last level was ‘1’, and pull-down if the last level was ‘0’.
Figure 15-4. I/O configuration - Totem-pole with bus-keeper. DIRn OUTn Pn INn 15.3.5 Others Figure 15-5. Output configuration - Wired-OR with optional pull-down. OUTn Pn INn Figure 15-6. I/O configuration - Wired-AND with optional pull-up.
15.4 Input sensing Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is shown in Figure 15-7. Figure 15-7. Input sensing system overview. Asynchronous sensing EDGE DETECT Interrupt Control IREQ Synchronous sensing Pn Synchronizer INn D Q D Q INVERTED I/O R EDGE DETECT Event R When a pin is configured with inverted I/O, the pin value is inverted before the input sensing. 15.
16. TC0/1 – 16-bit Timer/Counter Type 0 and 1 16.
There are two differences between timer/counter type 0 and type 1. Timer/counter 0 has four CC channels, and timer/counter 1 has two CC channels. All information related to CC channels 3 and 4 is valid only for timer/counter 0. Only Timer/Counter 0 has the split mode feature that split it into two 8-bit Timer/Counters with four compare channels each. Some timer/counters have extensions to enable more specialized waveform and frequency generation.
17. TC2 - Timer/Counter Type 2 17.
18. AWeX – Advanced Waveform Extension 18.
19. Hi-Res – High Resolution Extension 19.1 Features z Increases waveform generator resolution up to 8x (three bits) z Supports frequency, single-slope PWM, and dual-slope PWM generation z Supports the AWeX when this is used for the same timer/counter 19.2 Overview The high-resolution (hi-res) extension can be used to increase the resolution of the waveform generation output from a timer/counter by four or eight.
20. RTC – 16-bit Real-Time Counter 20.1 Features z 16-bit resolution z Selectable clock source 32.768kHz external crystal External clock z 32.768kHz internal oscillator z 32kHz internal ULP oscillator z z z Programmable 10-bit clock prescaling z One compare register z One period register z Clear counter on period overflow z Optional interrupt/event on overflow and compare match 20.
21. USB – Universal Serial Bus Interface 21.1 Features z One USB 2.0 full speed (12Mbps) and low speed (1.
Multipacket transfer enables a data payload exceeding the maximum packet size of an endpoint to be transferred as multiple packets without software intervention. This reduces the CPU intervention and the interrupts needed for USB transfers. For low-power operation, the USB module can put the microcontroller into any sleep mode when the USB bus is idle and a suspend condition is given. Upon bus resumes, the USB module can wake up the microcontroller from any sleep mode. PORTD has one USB.
22. TWI – Two-Wire Interface 22.
PORTC and PORTE each has one TWI. Notation of these peripherals are TWIC and TWIE. 23. SPI – Serial Peripheral Interface 23.1 Features z Two Identical SPI peripherals z Full-duplex, three-wire synchronous data transfer z Master or slave operation z Lsb first or msb first data transfer z Eight programmable bit rates z Interrupt flag at the end of transmission z Write collision flag to indicate data collision z Wake up from idle sleep mode z Double speed master mode 23.
24. USART 24.
25. IRCOM – IR Communication Module 25.1 Features z Pulse modulation/demodulation for infrared communication z IrDA compatible for baud rates up to 115.2Kbps z Selectable pulse modulation scheme 3/16 of the baud rate period Fixed pulse period, 8-bit programmable z Pulse modulation disabled z z z Built-in filtering z Can be connected to and used by any USART 25.2 Overview Atmel AVR XMEGA devices contain an infrared communication module (IRCOM) that is IrDA compatible for baud rates up to 115.2Kbps.
26. AES and DES Crypto Engine 26.1 Features z Data Encryption Standard (DES) CPU instruction z Advanced Encryption Standard (AES) crypto module z DES Instruction Encryption and decryption DES supported z Encryption/decryption in 16 CPU clock cycles per 8-byte block z z z AES crypto module Encryption and decryption Supports 128-bit keys z Supports XOR data load mode to the state memory z Encryption/decryption in 375 clock cycles per 16-byte block z z 26.
27. CRC – Cyclic Redundancy Check Generator 27.
28. ADC – 12-bit Analog to Digital Converter 28.1 Features z One Analog to Digital Converter (ADC) z 12-bit resolution z Up to two million samples per second Two inputs can be sampled simultaneously using ADC and 1x gain stage Four inputs can be sampled within 1.5µs z Down to 2.5µs conversion time with 8-bit resolution z Down to 3.
Figure 28-1. ADC overview. ADC0 Compare • •• ADC11 ADC0 Internal signals VINP CH0 Result •• • ADC7 ADC4 CH1 Result Threshold (Int Req) ½x - 64x CH2 Result • •• ADC7 Int. signals < > Internal signals CH3 Result VINN ADC0 • •• ADC3 Int. signals Internal 1.00V Internal AVCC/1.6V Internal AVCC/2 AREFA AREFB Reference Voltage Two inputs can be sampled simultaneously as both the ADC and the gain stage include sample and hold circuits, and the gain stage has 1x gain setting.
29. DAC – 12-bit Digital to Analog Converter 29.1 Features z One Digital to Analog Converter (DAC) z 12-bit resolution z Two independent, continuous-drive output channels z Up to one million samples per second conversion rate per DAC channel z Built-in calibration that removes: z z 29.
A DAC conversion is automatically started when new data to be converted are available. Events from the event system can also be used to trigger a conversion, and this enables synchronized and timed conversions between the DAC and other peripherals, such as a timer/counter. The DMA controller can be used to transfer data to the DAC. The DAC has high drive strength, and is capable of driving both resistive and capacitive loads, aswell as loads which combine both.
30. AC – Analog Comparator 30.
Figure 30-1. Analog comparator overview. Pin Input AC0OUT Pin Input Hysteresis Enable DAC Voltage Scaler ACnMUXCTRL ACnCTRL Interrupt Mode WINCTRL Enable Bandgap Interrupt Sensititivity Control & Window Function Interrupts Events Hysteresis Pin Input AC1OUT Pin Input The window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in Figure 30-2. Figure 30-2. Analog comparator window function.
31. Programming and Debugging 31.
32.1.1 Operation/Power Supply VCC Digital supply voltage AVCC Analog supply voltage GND Ground 32.1.2 Port Interrupt functions SYNC Port pin with full synchronous and limited asynchronous interrupt function ASYNC Port pin with full synchronous and full asynchronous interrupt function 32.1.
32.1.
32.2 Alternate Pin Functions The tables below show the primary/default function for each pin on a port in the first column, the pin number in the second column, and then all alternate pin functions in the remaining columns. The head row shows what peripheral that enable and use the alternate pin functions. For better flexibility, some alternate functions also have selectable pin locations for their functions, this is noted under the first table where this apply. Table 32-1. Port A - alternate functions.
Table 32-3. Port C - alternate functions. PORT C PIN # INTERRUPT TCC0 AWEXC TCC1 (1)(2) USART C0(3) USART C1 SPIC(4) TWIC TWIC w/ext driver GND 8 VCC 9 PC0 10 SYNC OC0A OC0ALS PC1 11 SYNC OC0B OC0AHS XCK0 PC2 12 SYNC/ ASYNC OC0C OC0BLS RXD0 SDAOUT PC3 13 SYNC OC0D OC0BHS TXD0 SCLOUT PC4 14 SYNC OC0CLS OC1A PC5 15 SYNC OC0CHS OC1B PC6 16 SYNC PC7 17 SYNC Notes: 1. 2. 3. 4. 5. 6.
Table 32-5. Port E - alternate functions. PORT E PIN # INTERRUPT TCE0 USARTE0 PE0 28 SYNC OC0A PE1 29 SYNC OC0B XCK0 GND 30 VCC 31 PE2 32 SYNC/ASYNC OC0C RXD0 PE3 33 SYNC OC0D TXD0 TWIE SDA SCL Table 32-6. Port R - alternate functions. PORT R PIN # INTERRUPT PDI XTAL TOSC(1) PDI 34 PDI_DATA RESET 35 PDI_CLOCK PR0 36 SYNC XTAL2 TOSC2 PR1 37 SYNC XTAL1 TOSC1 Note: 1. TOSC pins can optionally be moved to PE2/PE3.
33. Peripheral Module Address Map The address maps show the base address for each peripheral and module in Atmel AVR XMEGA A4U. For complete register description and summary for each peripheral module, refer to the XMEGA AU manual. Table 33-1. Peripheral module address map.
Base address Name Description 0x0620 PORTB Port B 0x0640 PORTC Port C 0x0660 PORTD Port D 0x0680 PORTE Port E 0x07E0 PORTR Port R 0x0800 TCC0 Timer/Counter 0 on port C 0x0840 TCC1 Timer/Counter 1 on port C 0x0880 AWEXC Advanced Waveform Extension on port C 0x0890 HIRESC High Resolution Extension on port C 0x08A0 USARTC0 USART 0 on port C 0x08B0 USARTC1 USART 1 on port C 0x08C0 SPIC 0x08F8 IRCOM 0x0900 TCD0 Timer/Counter 0 on port D 0x0940 TCD1 Timer/Counter 1 on
34.
Mnemonic s Operand s Description RCALL k Relative Call Subroutine Operation Flags #Clock s PC ← PC + k + 1 None 2 / 3 (1) ICALL Indirect Call to (Z) PC(15:0) PC(21:16) ← ← Z, 0 None 2 / 3 (1) EICALL Extended Indirect Call to (Z) PC(15:0) PC(21:16) ← ← Z, EIND None 3 (1) call Subroutine PC ← k None 3 / 4 (1) RET Subroutine Return PC ← STACK None 4 / 5 (1) RETI Interrupt Return PC ← STACK I 4 / 5 (1) if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3 CALL k CPSE R
Mnemonic s Operand s Description MOVW Rd, Rr Copy Register Pair LDI Rd, K LDS Operation Flags #Clock s Rd+1:Rd ← Rr+1:Rr None 1 Load Immediate Rd ← K None 1 Rd, k Load Direct from data space Rd ← (k) None 2 (1)(2) LD Rd, X Load Indirect Rd ← (X) None 1 (1)(2) LD Rd, X+ Load Indirect and Post-Increment Rd X ← ← (X) X+1 None 1 (1)(2) LD Rd, -X Load Indirect and Pre-Decrement X ← X - 1, Rd ← (X) ← ← X-1 (X) None 2 (1)(2) LD Rd, Y Load Indirect Rd ← (Y)
Mnemonic s Operand s ELPM Rd, Z+ SPM Description Operation Flags #Clock s Rd Z ← ← (RAMPZ:Z), Z+1 None 3 Store Program Memory (RAMPZ:Z) ← R1:R0 None - (RAMPZ:Z) Z ← ← R1:R0, Z+2 None - Rd ← I/O(A) None 1 I/O(A) ← Rr None 1 STACK ← Rr None 1 (1) Extended Load Program Memory and PostIncrement SPM Z+ Store Program Memory and Post-Increment by 2 IN Rd, A In From I/O Location OUT A, Rr Out To I/O Location PUSH Rr Push Register on Stack POP Rd Pop Register fr
Mnemonic s Operand s Description Operation Flags #Clock s Z ← 0 Z 1 Global Interrupt Enable I ← 1 I 1 CLI Global Interrupt Disable I ← 0 I 1 SES Set Signed Test Flag S ← 1 S 1 CLS Clear Signed Test Flag S ← 0 S 1 SEV Set Two’s Complement Overflow V ← 1 V 1 CLV Clear Two’s Complement Overflow V ← 0 V 1 SET Set T in SREG T ← 1 T 1 CLT Clear T in SREG T ← 0 T 1 SEH Set Half Carry Flag in SREG H ← 1 H 1 CLH Clear Half Carry Flag in SREG
35. Packaging information 35.1 44A PIN 1 IDENTIFIER PIN 1 e B E1 E A1 A2 D1 D C 0°~7° A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.
35.
35.3 44M1 D Marked Pin# 1 I D E SE ATING PLAN E A1 TOP VIE W A3 A K L Pin #1 Co rner D2 1 2 3 SIDE VIEW Pin #1 Triangle Option A E2 Option B K Option C b e Pin #1 Cham fer (C 0.30) Pin #1 Notch (0.20 R) B OT TOM VIE W COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 – 0.02 0.05 A3 0.20 REF b 0.18 0.23 0.30 D 6.90 7.00 7.10 D2 5.00 5.20 5.40 E 6.90 7.00 7.10 E2 5.00 5.20 5.40 e Note: JEDEC Standard MO-220, Fig .
35.4 49C2 E A1 BALL ID 0.10 D A1 TOP VIEW A A2 SIDE VIEW E1 G e F E D D1 COMMON DIMENSIONS (Unit of Measure = mm) C B 1 A1 BALL CORNER MIN NOM MAX A – – 1.00 A1 0.20 – – A2 0.65 – – D 4.90 5.00 5.10 SYMBOL A 2 3 4 5 b 6 7 e 49 - Ø0.35 ±0.05 BOTTOM VIEW D1 3.90 BSC E 4.90 5.00 5.10 E1 b NOTE 3.90 BSC 0.30 0.35 e 0.40 0.65 BSC 3/14/08 TITLE 49C2, 49-ball (7 x 7 array), 0.65mm pitch, Package Drawing Contact: packagedrawings@atmel.com 5.0 x 5.0 x 1.
36. Electrical Characteristics All typical values are measured at T = 25°C unless other temperature condition is given. All minimum and maximum values are valid across operating temperature and voltage unless other conditions are given. 36.1 ATxmega16A4U 36.1.1 Absolute Maximum Ratings Stresses beyond those listed in Table 36-1 may cause permanent damage to the device.
Table 36-3. Operating voltage and frequency. Symbol ClkCPU Parameter Condition CPU clock frequency Min. Typ. Max. VCC = 1.6V 0 12 VCC = 1.8V 0 12 VCC = 2.7V 0 32 VCC = 3.6V 0 32 Units MHz The maximum CPU clock frequency depends on VCC. As shown in Figure 36-1 the Frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V. Figure 36-1. Maximum Frequency vs. VCC. MHz 32 Safe Operating Area 12 1.6 1.8 2.7 3.
36.1.3 Current consumption Table 36-4. Current consumption for Active mode and sleep modes. Symbol Parameter Condition Min. 32kHz, Ext. Clk Active power consumption (1) 1MHz, Ext. Clk 2MHz, Ext. Clk VCC = 3.0V 80 VCC = 1.8V 230 VCC = 3.0V 480 VCC = 1.8V 430 600 0.9 1.4 9.6 12 VCC = 3.0V 3.9 VCC = 1.8V 62 VCC = 3.0V 118 VCC = 1.8V 125 225 240 350 3.8 5.5 0.1 1.0 1.2 4.5 T = 105°C 3.5 6.0 WDT and Sampled BOD enabled, T = 25°C 1.3 3.0 2.4 6.0 4.5 8.0 1MHz, Ext.
Table 36-5. Current consumption for modules and peripherals. Symbol Parameter Condition (1) Min. Max. Units ULP oscillator 1.0 µA 32.768kHz int. oscillator 27 µA 2MHz int. oscillator 32MHz int. oscillator PLL 85 DFLL enabled with 32.768kHz int. osc. as reference BOD µA 115 270 DFLL enabled with 32.768kHz int. osc. as reference 20x multiplication factor, 32MHz int. osc. DIV4 as reference Watchdog timer ICC Typ. µA 460 220 µA 1.
36.1.4 Wake-up time from sleep modes Table 36-6. Symbol Device wake-up time from sleep modes with various system clock sources. Parameter Wake-up time from idle, standby, and extended standby mode twakeup Wake-up time from power-save and power-down mode Note: 1. Condition Min. Typ. (1) External 2MHz clock 2.0 32.768kHz internal oscillator 120 2MHz internal oscillator 2.0 32MHz internal oscillator 0.2 External 2MHz clock 4.5 32.768kHz internal oscillator 320 2MHz internal oscillator 9.
36.1.5 I/O Pin Characteristics The I/O pins comply with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification. Table 36-7. I/O pin characteristics. Symbol IOH (1)/ IOL (2) Parameter Condition Max. Units -20 20 mA VCC = 2.7 - 3.6V 2.0 VCC+0.3 VCC = 2.0 - 2.7V 0.7*VCC VCC+0.3 VCC = 1.6 - 2.0V 0.8*VCC VCC+0.3 VCC = 2.7- 3.6V -0.3 0.8 VCC = 2.0 - 2.7V -0.3 0.3*VCC VCC = 1.6 - 2.0V -0.3 0.
36.1.6 ADC characteristics Table 36-8. Power supply, reference and input range. Symbol Parameter AVCC Analog supply voltage VREF Reference voltage Condition Min. Typ. Max. Units VCC- 0.3 VCC+ 0.3 V 1.0 AVCC- 0.6 V Rin Input resistance Switched 4.0 kΩ Csample Input capacitance Switched 4.4 pF RAREF Reference input resistance (leakage only) >10 MΩ CAREF Reference input capacitance Static load 7.
Table 36-10. Accuracy characteristics. Symbol Parameter Condition (2) RES Resolution Programmable to 8 or 12 bit Min. Typ. Max. Units 8 12 12 Bits VCC-1.0V < VREF< VCC-0.6V ±1.2 ±2.0 All VREF ±1.5 ±3.0 VCC-1.0V < VREF< VCC-0.6V ±1.0 ±2.0 All VREF ±1.5 ±3.0 guaranteed monotonic <±0.8 <±1.0 500ksps INL (1) Integral non-linearity 2000ksps DNL (1) Differential non-linearity Offset error mV Temperature drift <0.01 mV/K Operating voltage drift <0.
Symbol Parameter Offset error, input referred Condition Min. Typ. 1x gain, normal mode -2 8x gain, normal mode -5 64x gain, normal mode -4 1x gain, normal mode Noise 1. Units mV 0.5 VCC = 3.6V Ext. VREF 8x gain, normal mode mV rms 1.5 64x gain, normal mode Note: Max. 11 Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range. 36.1.7 DAC Characteristics Table 36-12. Power supply, reference and output range.
Table 36-13. Clock and timing. Symbol fDAC Parameter Conversion rate Condition Cload=100pF, maximum step size Min. Normal mode Typ. 0 Max. 1000 Low power mode 500 Units ksps Table 36-14. Accuracy characteristics. Symbol RES Parameter Condition Typ. Input resolution VREF= Ext 1.0V INL (1) Integral non-linearity VREF=AVCC VREF=INT1V VREF=Ext 1.0V DNL (1) Differential non-linearity VREF=AVCC VREF=INT1V Gain error After calibration Gain calibration step size 1. Max.
36.1.8 Analog Comparator Characteristics Table 36-15. Analog Comparator characteristics. Symbol Voff Ilk Parameter Condition Min. Typ. Max. Units Input offset voltage <±10 mV Input leakage current <1.0 nA Input voltage range -0.1 AVCC V AC startup time 100 µs Vhys1 Hysteresis, none 0 mV Vhys2 Hysteresis, small Vhys3 Hysteresis, large mode = High Speed (HS) 13 mode = Low Power (LP) 30 mode = HS 30 mode = LP 60 VCC = 3.
36.1.10 Brownout Detection Characteristics Table 36-17. Brownout detection characteristics. Symbol Parameter Condition BOD level 0 falling VCC VBOT tBOD Typ. Max. 1.60 1.62 1.72 BOD level 1 falling VCC 1.8 BOD level 2 falling VCC 2.0 BOD level 3 falling VCC 2.2 BOD level 4 falling VCC 2.4 BOD level 5 falling VCC 2.6 BOD level 6 falling VCC 2.8 BOD level 7 falling VCC 3.0 Continuous mode Detection time VHYST Min. V 0.4 Sampled mode µs 1000 Hysteresis Units 1.2 % 36.1.
36.1.13 Flash and EEPROM Memory Characteristics Table 36-20. Endurance and data retention. Symbol Parameter Condition Write/Erase cycles Flash Data retention Write/Erase cycles EEPROM Data retention Min. 25°C 10K 85°C 10K 105°C 2K 25°C 100 85°C 25 105°C 10 25°C 100K 85°C 100K 105°C 30K 25°C 100 85°C 25 105°C 10 Typ. Max. Units Cycle Year Cycle Year Table 36-21. Programming time. Symbol Parameter Typ.(1) Max.
36.1.14 Clock and Oscillator Characteristics 36.1.14.1 Calibrated 32.768kHz Internal Oscillator characteristics Table 36-22. 32.768kHz internal oscillator characteristics. Symbol Parameter Condition Min. Frequency Factory calibration accuracy Typ. Max. 32.768 T = 85°C, VCC = 3.0V User calibration accuracy Units kHz -0.5 0.5 % -0.5 0.5 % Max. Units 2.2 MHz 36.1.14.2 Calibrated 2MHz RC Internal Oscillator characteristics Table 36-23. 2MHz internal oscillator characteristics.
36.1.14.5 Internal Phase Locked Loop (PLL) characteristics Table 36-26. Internal PLL characteristics. Symbo l fIN Input frequency fOUT Note: Parameter Output frequency (1) 1. Condition Min. Output frequency must be within fOUT Typ. Max. Units 0.4 64 MHz VCC= 1.6 - 1.8V 20 48 VCC= 2.7 - 3.6V 20 128 MHz Start-up time 25 µs Re-lock time 25 µs The maximum output frequency vs. supply voltage is linear between 1.8V and 2.
Table 36-28. External clock with prescaler (1)for system clock. Symbol 1/tCK Parameter Condition Clock Frequency (2) tCK Clock Period tCH Clock High Time tCL Clock Low Time tCR Rise Time (for maximum frequency) tCF Fall Time (for maximum frequency) ΔtCK Notes: Min. Typ. VCC = 1.6 - 1.8V 0 90 VCC = 2.7 - 3.6V 0 142 VCC = 1.6 - 1.8V 11 VCC = 2.7 - 3.6V 7 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 Units MHz ns ns ns VCC = 1.6 - 1.
Symbol Parameter Duty cycle Condition XOSCPWR=0 Min. FRQRANGE=0 40 FRQRANGE=1 42 FRQRANGE=2 or 3 45 XOSCPWR=1 2.4k 1MHz crystal, CL=20pF 8.7k 2MHz crystal, CL=20pF 2.1k 2MHz crystal 4.
36.1.14.8 External 32.768kHz crystal oscillator and TOSC characteristics Table 36-30. External 32.768kHz crystal oscillator and TOSC characteristics. Symbol Parameter Condition ESR/R1 Recommended crystal equivalent series resistance (ESR) CTOSC1 Parasitic capacitance TOSC1 pin CTOSC2 Parasitic capacitance TOSC2 pin Recommended safety factor Note: 1. Min. Typ. Max. Crystal load capacitance 6.5pF 60 Crystal load capacitance 9.0pF 35 5.4 Alternate TOSC location 4.0 7.
36.1.15 SPI Characteristics Figure 36-5. SPI timing requirements in master mode. SS tMOS tSCKR tSCKF SCK (CPOL = 0) tSCKW SCK (CPOL = 1) tSCKW tMIS MISO (Data input) tMIH tSCK MSB LSB tMOH MOSI (Data output) tMOH MSB LSB Figure 36-6. SPI timing requirements in slave mode.
Table 36-31. SPI timing characteristics and requirements. Symbol Parameter Condition Min. Typ. Max. tSCK SCK period Master (See Table 21-4 in XMEGA AU Manual) tSCKW SCK high/low width Master 0.5*SCK tSCKR SCK rise time Master 2.7 tSCKF SCK fall time Master 2.7 tMIS MISO setup to SCK Master 10 tMIH MISO hold after SCK Master 10 tMOS MOSI setup SCK Master 0.
Table 36-32. Two-wire interface characteristics. Symbol Parameter Condition Min. Typ. Max. Units VIH Input high voltage 0.7*VCC VCC+0.5 V VIL Input low voltage 0.5 0.3*VCC V Vhys Hysteresis of Schmitt trigger inputs VOL Output low voltage tr Rise time for both SDA and SCL tof Output fall time from VIHmin to VILmax tSP Spikes suppressed by input filter II Input current for each I/O Pin CI Capacitance for each I/O Pin fSCL SCL clock frequency 0.
36.2 ATxmega32A4U 36.2.1 Absolute Maximum Ratings Stresses beyond those listed in Table 36-33 may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 36-33. Absolute maximum ratings. Symbol Parameter Condition Min. Typ. -0.
Figure 36-8. Maximum Frequency vs. VCC. MHz 32 Safe Operating Area 12 1.6 1.8 2.7 3.
36.2.3 Current consumption Table 36-36. Current consumption for Active mode and sleep modes. Symbol Parameter Condition Min. 32kHz, Ext. Clk Active power consumption(1) 1MHz, Ext. Clk 2MHz, Ext. Clk 40 VCC = 3.0V 80 VCC = 1.8V 230 VCC = 3.0V 480 VCC = 1.8V 430 600 0.9 1.4 9.6 12 2.4 VCC = 3.0V 3.9 VCC = 1.8V 62 VCC = 3.0V 118 VCC = 1.8V 125 225 240 350 3.8 5.5 0.1 1.0 1.2 4.5 T = 105°C 3.5 6.0 WDT and sampled BOD enabled, T = 25°C 1.3 3.0 2.4 6.0 4.5 8.
Table 36-37. Current consumption for modules and peripherals. Symbol Parameter Condition (1) Min. Max. Units ULP oscillator 1.0 µA 32.768kHz int. oscillator 27 µA 2MHz int. oscillator 32MHz int. oscillator PLL 85 DFLL enabled with 32.768kHz int. osc. as reference BOD µA 115 270 DFLL enabled with 32.768kHz int. osc. as reference 20x multiplication factor, 32MHz int. osc. DIV4 as reference Watchdog timer ICC Typ. µA 460 220 µA 1.
36.2.4 Wake-up time from sleep modes Table 36-38. Device wake-up time from sleep modes with various system clock sources. Symbol Parameter Wake-up time from idle, standby, and extended standby mode twakeup Wake-up time from power-save and power-down mode Note: 1. Condition Min. Typ. (1) External 2MHz clock 2.0 32.768kHz internal oscillator 120 2MHz internal oscillator 2.0 32MHz internal oscillator 0.2 External 2MHz clock 4.5 32.768kHz internal oscillator 320 2MHz internal oscillator 9.
36.2.5 I/O Pin Characteristics The I/O pins comply with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification. Table 36-39. I/O pin characteristics. Symbol IOH (1)/ Parameter Condition Max. Units -20 20 mA VCC = 2.7 - 3.6V 2.0 VCC+0.3 VCC = 2.0 - 2.7V 0.7*VCC VCC+0.3 VCC = 1.6 - 2.0V 0.8*VCC VCC+0.3 VCC = 2.7- 3.6V -0.3 0.8 VCC = 2.0 - 2.7V -0.3 0.3*VCC VCC = 1.6 - 2.0V -0.3 0.
36.2.6 ADC characteristics Table 36-40. Power supply, reference and input range. Symbol Parameter AVCC Analog supply voltage VREF Reference voltage Condition Min. Typ. Max. Units VCC- 0.3 VCC+ 0.3 V 1 AVCC- 0.6 V Rin Input resistance Switched 4.0 kΩ Csample Input capacitance Switched 4.
Table 36-42. Accuracy characteristics. Symbol Parameter Condition (2) Min. Typ. Max. Units RES Resolution Programmable to 8 or 12 bit 8 12 12 Bits VCC-1.0V < VREF< VCC-0.6V ±1.2 ±2.0 All VREF ±1.5 ±3.0 VCC-1.0V < VREF< VCC-0.6V ±1.0 ±2.0 All VREF ±1.5 ±3.0 guaranteed monotonic <±0.8 <±1.0 500ksps INL(1) Integral non-linearity 2000ksps DNL(1) Differential non-linearity Offset error mV Temperature drift <0.01 mV/K Operating voltage drift <0.
Symbol Parameter Condition Offset error, input referred Min. 1x gain, normal mode -2.0 8x gain, normal mode -5.0 64x gain, normal mode -4.0 1x gain, normal mode Noise 1. Max. Units mV 0.5 VCC = 3.6V 8x gain, normal mode 64x gain, normal mode Note: Typ. mV rms 1.5 Ext. VREF 11 Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range. 36.2.7 DAC Characteristics Table 36-44. Power supply, reference and output range.
Table 36-46. Accuracy characteristics. Symbol RES Parameter Condition Typ. Input resolution VREF= Ext 1.0V INL (1) Integral non-linearity VREF=AVCC VREF=INT1V VREF=Ext 1.0V DNL (1) Differential non-linearity VREF=AVCC VREF=INT1V Gain error After calibration Gain calibration step size 1. Max. Units 12 Bits VCC = 1.6V ±2.0 ±3.0 VCC = 3.6V ±1.5 ±2.5 VCC = 1.6V ±2.0 ±4.0 VCC = 3.6V ±1.5 ±4.0 VCC = 1.6V ±5.0 VCC = 3.6V ±5.0 VCC = 1.6V ±1.5 3.0 VCC = 3.6V ±0.6 1.
36.2.8 Analog Comparator Characteristics Table 36-47. Analog Comparator characteristics. Symbol Voff Parameter Condition Min. Input offset voltage Ilk Input leakage current Input voltage range Typ. Max. Units <±10 mV <1 nA -0.1 AVCC V AC startup time 100 µs Vhys1 Hysteresis, none 0 mV Vhys2 Hysteresis, small Vhys3 Hysteresis, large mode = High Speed (HS) 13 mode = Low Power (LP) 30 mode = HS 30 mode = LP 60 VCC = 3.
36.2.10 Brownout Detection Characteristics Table 36-49. Brownout detection characteristics. Symbol Parameter Condition BOD level 0 falling VCC VBOT tBOD Typ. Max. 1.60 1.62 1.72 BOD level 1 falling VCC 1.8 BOD level 2 falling VCC 2.0 BOD level 3 falling VCC 2.2 BOD level 4 falling VCC 2.4 BOD level 5 falling VCC 2.6 BOD level 6 falling VCC 2.8 BOD level 7 falling VCC 3.0 Detection time VHYST Min. Continuous mode V 0.4 Sampled mode µs 1000 Hysteresis Units 1.2 % 36.2.
36.2.13 Flash and EEPROM Memory Characteristics Table 36-52. Endurance and data retention. Symbol Parameter Condition Write/Erase cycles Flash Data retention Write/Erase cycles EEPROM Data retention Min. Typ. 25°C 10K 85°C 10K 105°C 2K 25°C 100 85°C 25 105°C 10 25°C 100K 85°C 100K 105°C 30K 25°C 100 85°C 25 105°C 10 Max. Units Cycle Year Cycle Year Table 36-53. Programming time. Symbol Parameter Typ.(1) Max.
36.2.14 Clock and Oscillator Characteristics 36.2.14.1 Calibrated 32.768kHz Internal Oscillator characteristics Table 36-54. 32.768kHz internal oscillator characteristics. Symbol Parameter Condition Min. Frequency Factory calibration accuracy Typ. Max. 32.768 T = 85°C, VCC = 3.0V User calibration accuracy Units kHz -0.5 0.5 % -0.5 0.5 % Max. Units 2.2 MHz 36.2.14.2 Calibrated 2MHz RC Internal Oscillator characteristics Table 36-55. 2MHz internal oscillator characteristics.
36.2.14.5 Internal Phase Locked Loop (PLL) characteristics Table 36-58. Internal PLL characteristics. Symbo l fIN Input frequency Output frequency (1) fOUT Note: Parameter 1. Condition Min. Output frequency must be within fOUT Typ. Max. Units 0.4 64 MHz VCC= 1.6 - 1.8V 20 48 VCC= 2.7 - 3.6V 20 128 MHz Start-up time 25 µs Re-lock time 25 µs The maximum output frequency vs. supply voltage is linear between 1.8V and 2.
Table 36-60. External clock with prescaler (1)for system clock. Symbol Parameter Condition Clock Frequency (2) 1/tCK tCK Clock Period tCH Clock High Time tCL Clock Low Time tCR Rise Time (for maximum frequency) tCF Fall Time (for maximum frequency) ΔtCK Notes: Min. Typ. VCC = 1.6 - 1.8V 0 90 VCC = 2.7 - 3.6V 0 142 VCC = 1.6 - 1.8V 11 VCC = 2.7 - 3.6V 7 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 Units MHz ns ns ns VCC = 1.6 - 1.
Symbol Parameter Condition 0.4MHz resonator, CL=100pF 2.4k 1MHz crystal, CL=20pF 8.7k 2MHz crystal, CL=20pF 2.1k 2MHz crystal 4.
36.2.14.8 External 32.768kHz crystal oscillator and TOSC characteristics Table 36-62. External 32.768kHz crystal oscillator and TOSC characteristics. Symbol Parameter Condition ESR/R1 Recommended crystal equivalent series resistance (ESR) CTOSC1 Parasitic capacitance TOSC1 pin CTOSC2 Parasitic capacitance TOSC2 pin Recommended safety factor Note: 1. Min. Typ. Max. Crystal load capacitance 6.5pF 60 Crystal load capacitance 9.0pF 35 5.4 Alternate TOSC location 4.0 7.
36.2.15 SPI Characteristics Figure 36-12. SPI timing requirements in master mode. SS tMOS tSCKR tSCKF SCK (CPOL = 0) tSCKW SCK (CPOL = 1) tSCKW tMIS MISO (Data input) tMIH tSCK MSB LSB tMOH MOSI (Data output) tMOH MSB LSB Figure 36-13. SPI timing requirements in slave mode.
Table 36-63. SPI timing characteristics and requirements. Symbol Parameter Condition Min. Typ. Max. tSCK SCK period Master (See Table 21-4 in XMEGA AU Manual) tSCKW SCK high/low width Master 0.5×SCK tSCKR SCK rise time Master 2.7 tSCKF SCK fall time Master 2.7 tMIS MISO setup to SCK Master 10 tMIH MISO hold after SCK Master 10 tMOS MOSI setup SCK Master 0.5×SCK tMOH MOSI hold after SCK Master 1.
36.2.16 Two-Wire Interface Characteristics Table 36-64 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel AVR XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 36-14. Figure 36-14. Two-wire interface bus timing. tof tHIGH tLOW tr SCL tSU;STA tHD;STA tHD;DAT tSU;STO tSU;DAT SDA tBUF Table 36-64. Two-wire interface characteristics. Symbol Parameter Condition Min. Typ. Max.
Symbol Parameter tHD;DAT Data hold time tSU;DAT Data setup time tSU;STO Setup time for STOP condition Bus free time between a STOP and START condition tBUF Notes: 1. 2. 3. Condition Min. Typ. Max. fSCL ≤ 100kHz 0 3.45 fSCL > 100kHz 0 0.9 fSCL ≤ 100kHz 250 fSCL > 100kHz 100 fSCL ≤ 100kHz 4.0 fSCL > 100kHz 0.6 fSCL ≤ 100kHz 4.7 fSCL > 100kHz 1.3 Units µs ns µs µs Required only for fSCL > 100kHz. Cb = Capacitance of one bus line in pF. fPER = Peripheral clock frequency.
36.3 ATxmega64A4U 36.3.1 Absolute Maximum Ratings Stresses beyond those listed in Table 36-65 may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 36-65. Absolute maximum ratings. Symbol Parameter Condition Min. Typ. -0.
Figure 36-15.Maximum Frequency vs. VCC. MHz 32 Safe Operating Area 12 1.6 1.8 2.7 3.
36.3.3 Current consumption Table 36-68. Current consumption for Active mode and sleep modes. Symbol Parameter Condition Min. 32kHz, Ext. Clk Active power consumption (1) 1MHz, Ext. Clk 2MHz, Ext. Clk VCC = 3.0V 132 VCC = 1.8V 223 VCC = 3.0V 476 VCC = 1.8V 400 600 0.8 1.4 8.2 12 VCC = 3.0V 3.5 VCC = 1.8V 57 VCC = 3.0V 110 VCC = 1.8V 115 225 216 350 3.5 5.5 0.1 1.0 1.2 4.5 T = 105°C 2.4 6.0 WDT and Sampled BOD enabled, T = 25°C 1.4 3.0 2.4 6.0 3.5 8.0 1MHz, Ext.
Table 36-69. Current consumption for modules and peripherals. Symbol Parameter Condition (1) Min. Max. Units ULP oscillator 1.0 µA 32.768kHz int. oscillator 29 µA 2MHz int. oscillator 32MHz int. oscillator PLL 85 DFLL enabled with 32.768kHz int. osc. as reference BOD 120 300 DFLL enabled with 32.768kHz int. osc. as reference 20x multiplication factor, 32MHz int. osc. DIV4 as reference Watchdog timer ICC Typ. 465 µA µA 320 µA 1.
36.3.4 Wake-up time from sleep modes Table 36-70. Device wake-up time from sleep modes with various system clock sources. Symbol Parameter Wake-up time from idle, standby, and extended standby mode twakeup Wake-up time from power-save and power-down mode Note: 1. Condition Min. Typ. (1) External 2MHz clock 2.0 32.768kHz internal oscillator 120 2MHz internal oscillator 2.0 32MHz internal oscillator 0.2 External 2MHz clock 4.5 32.768kHz internal oscillator 320 2MHz internal oscillator 9.
36.3.5 I/O Pin Characteristics The I/O pins comply with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification. Table 36-71. I/O pin characteristics. Symbol IOH (1)/ IOL (2) Parameter Condition Max. Units -20 20 mA VCC = 2.7- 3.6V 2.0 VCC+0.3 VCC = 2.0 - 2.7V 0.7*VCC VCC+0.3 VCC = 1.6 - 2.0V 0.8*VCC VCC+0.3 VCC = 2.7- 3.6V -0.3 0.8 VCC = 2.0 - 2.7V -0.3 0.3*VCC VCC = 1.6 - 2.0V -0.3 0.
36.3.6 ADC characteristics Table 36-72. Power supply, reference and input range. Symbol Parameter AVCC Analog supply voltage VREF Reference voltage Condition Min. Typ. Max. Units VCC- 0.3 VCC+ 0.3 V 1.0 AVCC- 0.6 V Rin Input resistance Switched 4.0 kΩ Csample Input capacitance Switched 4.4 pF RAREF Reference input resistance (leakage only) >10 MΩ CAREF Reference input capacitance Static load 7.
Table 36-74. Accuracy characteristics. Symbol Parameter Condition (2) RES Resolution Programmable to 8 or 12 bit Min. Typ. Max. Units 8 12 12 Bits VCC-1.0V < VREF< VCC-0.6V ±1.2 ±2 All VREF ±1.5 ±3 VCC-1.0V < VREF< VCC-0.6V ±1.0 ±2 All VREF ±1.5 ±3 guaranteed monotonic <±0.8 <±1 500ksps INL (1) Integral non-linearity 2000ksps DNL (1) Differential non-linearity Offset error mV Temperature drift <0.01 mV/K Operating voltage drift <0.
Symbol Parameter Condition Offset error, input referred Min. Typ. 1x gain, normal mode -2 8x gain, normal mode -5 64x gain, normal mode -4 1x gain, normal mode Noise 1. Units mV 0.5 VCC = 3.6V Ext. VREF 8x gain, normal mode mV rms 1.5 64x gain, normal mode Note: Max. 11 Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range. 36.3.7 DAC Characteristics Table 36-76. Power supply, reference and output range.
Table 36-78. Accuracy characteristics. Symbol RES Parameter Condition Typ. Input resolution VREF= Ext 1.0V INL (1) Integral non-linearity VREF=AVCC VREF=INT1V VREF=Ext 1.0V DNL (1) Differential non-linearity VREF=AVCC VREF=INT1V Gain error After calibration Gain calibration step size 1. Max. Units 12 Bits VCC = 1.6V ±2.0 ±3.0 VCC = 3.6V ±1.5 ±2.5 VCC = 1.6V ±2.0 ±4.0 VCC = 3.6V ±1.5 ±4.0 VCC = 1.6V ±5.0 VCC = 3.6V ±5.0 VCC = 1.6V ±1.5 3.0 VCC = 3.6V ±0.6 1.
36.3.8 Analog Comparator Characteristics Table 36-79. Analog Comparator characteristics. Symbol Voff Parameter Condition Min. Input offset voltage Ilk Input leakage current Input voltage range Typ. Max. Units <±10 mV <1 nA -0.1 AVCC V AC startup time 100 µs Vhys1 Hysteresis, none 0 mV Vhys2 Hysteresis, small Vhys3 Hysteresis, large mode = High Speed (HS) 20 mode = Low Power (LP) 30 mode = HS 35 mode = LP 60 VCC = 3.
36.3.10 Brownout Detection Characteristics Table 36-81. Brownout detection characteristics. Symbol Parameter Condition BOD level 0 falling VCC VBOT tBOD Typ. Max. 1.50 1.62 1.72 BOD level 1 falling VCC 1.8 BOD level 2 falling VCC 2.0 BOD level 3 falling VCC 2.2 BOD level 4 falling VCC 2.4 BOD level 5 falling VCC 2.6 BOD level 6 falling VCC 2.8 BOD level 7 falling VCC 3.0 Continuous mode Detection time VHYST Min. V 0.4 Sampled mode µs 1000 Hysteresis Units 1.2 % 36.3.
36.3.13 Flash and EEPROM Memory Characteristics Table 36-84. Endurance and data retention. Symbol Parameter Condition Write/Erase cycles Flash Data retention Write/Erase cycles EEPROM Data retention Min. 25°C 10K 85°C 10K 105°C 2K 25°C 100 85°C 25 105°C 10 25°C 100K 85°C 100K 105°C 30K 25°C 100 85°C 25 105°C 10 Typ. Max. Units Cycle Year Cycle Year Table 36-85. Programming time. Symbol Parameter 64KB Flash, EEPROM Application Erase EEPROM 1. 2.
36.3.14 Clock and Oscillator Characteristics 36.3.14.1 Calibrated 32.768kHz Internal Oscillator characteristics Table 36-86. 32.768kHz internal oscillator characteristics. Symbol Parameter Condition Min. Frequency Factory calibration accuracy Typ. Max. 32.768 T = 85°C, VCC = 3.0V User calibration accuracy Units kHz -0.5 0.5 % -0.5 0.5 % Max. Units 2.2 MHz 36.3.14.2 Calibrated 2MHz RC Internal Oscillator characteristics Table 36-87. 2MHz internal oscillator characteristics.
36.3.14.4 32kHz Internal ULP Oscillator characteristics Table 36-89. 32kHz internal ULP oscillator characteristics. Symbol Parameter Condition Min. Factory calibrated frequency Factory calibrated accuracy Typ. Max. 32 T = 85°C, VCC = 3.0V Accuracy Units kHz -12 12 % -30 30 % Max. Units MHz 36.3.14.5 Internal Phase Locked Loop (PLL) characteristics Table 36-90. Internal PLL characteristics. Symbo l fIN Input frequency Output frequency (1) fOUT Note: Parameter 1. Condition Min. Typ.
Symbol Parameter tCL Clock Low Time tCR Rise Time (for maximum frequency) tCF Fall Time (for maximum frequency) ΔtCK Note: Condition Min. VCC = 1.6 - 1.8V 30.0 VCC = 2.7 - 3.6V 12.5 Typ. Units ns VCC = 1.6 - 1.8V 10 VCC = 2.7 - 3.6V 3 VCC = 1.6 - 1.8V 10 VCC = 2.7 - 3.6V 3 Change in period from one clock cycle to the next 1. Max. 10 ns ns % The maximum frequency vs. supply voltage is linear between 1.6V and 2.
Symbol Parameter Long term jitter Condition XOSCPWR=0 Min. FRQRANGE=0 XOSCPWR=0 FRQRANGE=1, 2, or 3 XOSCPWR=0 FRQRANGE=0 <0.1 FRQRANGE=1 <0.05 FRQRANGE=2 or 3 <0.005 FRQRANGE=0 40 FRQRANGE=1 42 FRQRANGE=2 or 3 45 1MHz crystal, CL=20pF 8.7k 2MHz crystal, CL=20pF 2.1k 2MHz crystal 4.
Symbol Parameter Condition Min. ESR SF = Safety factor Typ. Max. Units min(RQ)/SF kΩ CXTAL1 Parasitic capacitance XTAL1 pin 5.60 pF CXTAL2 Parasitic capacitance XTAL2 pin 7.62 pF CLOAD Parasitic capacitance load 3.23 pF Note: 1. Numbers for negative impedance are not tested in production but guaranteed from design and characterization 36.3.14.8 External 32.768kHz crystal oscillator and TOSC characteristics Table 36-94. External 32.768kHz crystal oscillator and TOSC characteristics.
36.3.15 SPI Characteristics Figure 36-19.SPI timing requirements in master mode. SS tMOS tSCKR tSCKF SCK (CPOL = 0) tSCKW SCK (CPOL = 1) tSCKW tMIS MISO (Data input) tMIH tSCK MSB LSB tMOH MOSI (Data output) tMOH MSB LSB Figure 36-20.SPI timing requirements in slave mode.
Table 36-95. SPI timing characteristics and requirements. Symbol Parameter Condition Min. Typ. Max. tSCK SCK period Master (See Table 21-4 in XMEGA AU Manual) tSCKW SCK high/low width Master 0.5*SCK tSCKR SCK rise time Master 2.7 tSCKF SCK fall time Master 2.7 tMIS MISO setup to SCK Master 11 tMIH MISO hold after SCK Master 0 tMOS MOSI setup SCK Master 0.5*SCK tMOH MOSI hold after SCK Master 1.
36.3.16 Two-Wire Interface Characteristics Table 36-96 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel AVR XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 36-21. Figure 36-21.Two-wire interface bus timing. tof tHIGH tLOW tr SCL tSU;STA tHD;STA tHD;DAT tSU;STO tSU;DAT SDA tBUF Table 36-96. Two-wire interface characteristics. Symbol Parameter Condition Min. Typ. Max.
Symbol Parameter tHD;DAT Data hold time tSU;DAT Data setup time tSU;STO Setup time for STOP condition Bus free time between a STOP and START condition tBUF Notes: 1. 2. 3. Condition Min. Typ. Max. fSCL ≤ 100kHz 0 3.45 fSCL > 100kHz 0 0.9 fSCL ≤ 100kHz 250 fSCL > 100kHz 100 fSCL ≤ 100kHz 4.0 fSCL > 100kHz 0.6 fSCL ≤ 100kHz 4.7 fSCL > 100kHz 1.3 Units µs ns µs µs Required only for fSCL > 100kHz. Cb = Capacitance of one bus line in pF. fPER = Peripheral clock frequency.
36.4 ATxmega128A4U 36.4.1 Absolute Maximum Ratings Stresses beyond those listed in Table 36-97 may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 36-97. Absolute maximum ratings. Symbol Parameter Condition Min. Typ. -0.
Figure 36-22.Maximum Frequency vs. VCC. MHz 32 Safe Operating Area 12 1.6 1.8 2.7 3.
36.4.3 Current consumption Table 36-100.Current consumption for Active mode and sleep modes. Symbol Parameter Condition Min. 32kHz, Ext. Clk Active power consumption (1) 1MHz, Ext. Clk 2MHz, Ext. Clk 135 VCC = 1.8V 255 VCC = 3.0V 535 VCC = 1.8V 460 600 1.0 1.4 9.5 12 3.9 VCC = 1.8V 62 VCC = 3.0V 118 VCC = 1.8V 125 225 240 350 3.8 5.5 0.1 1.0 1.5 4.5 T = 105°C 0.1 8.6 WDT and Sampled BOD enabled, T = 25°C 1.4 3.0 2.8 6.0 1.4 8.8 1MHz, Ext. Clk VCC = 3.
Table 36-101.Current consumption for modules and peripherals. Symbol Parameter Condition (1) Min. µA 32.768kHz int. oscillator 29 µA PLL 85 DFLL enabled with 32.768kHz int. osc. as reference BOD µA 115 270 DFLL enabled with 32.768kHz int. osc. as reference 20x multiplication factor, 32MHz int. osc. DIV4 as reference Watchdog timer µA 440 320 µA 1.0 µA Continuous mode 138 Sampled mode, includes ULP oscillator 1.2 µA Internal 1.0V reference 260 µA Temperature sensor 250 µA 3.
36.4.4 Wake-up time from sleep modes Table 36-102. Device wake-up time from sleep modes with various system clock sources. Symbol Parameter Wake-up time from idle, standby, and extended standby mode twakeup Wake-up time from power-save and power-down mode Note: 1. Condition Min. Typ. (1) External 2MHz clock 2.0 32.768kHz internal oscillator 120 2MHz internal oscillator 2.0 32MHz internal oscillator 0.2 External 2MHz clock 4.5 32.768kHz internal oscillator 320 2MHz internal oscillator 9.
36.4.5 I/O Pin Characteristics The I/O pins comply with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification. Table 36-103.I/O pin characteristics. Symbol IOH (1)/ Parameter Condition Max. Units -20 20 mA VCC = 2.7 - 3.6V 2.0 VCC+0.3 VCC = 2.0 - 2.7V 0.7*VCC VCC+0.3 VCC = 1.6 - 2.0V 0.8*VCC VCC+0.3 VCC = 2.7- 3.6V -0.3 0.8 VCC = 2.0 - 2.7V -0.3 0.3*VCC VCC = 1.6 - 2.0V -0.3 0.
36.4.6 ADC characteristics Table 36-104.Power supply, reference and input range. Symbol Parameter AVCC Analog supply voltage VREF Reference voltage Rin Condition Min. Typ. Max. Units VCC- 0.3 VCC+ 0.3 V 1 AVCC- 0.6 V Input resistance Switched 4.0 kΩ Csample Input capacitance Switched 4.
Table 36-106. Accuracy characteristics. Symbol Parameter Condition (2) RES Resolution Programmable to 8 or 12 bit Min. Typ. Max. Units 8 12 12 Bits VCC-1.0V < VREF< VCC-0.6V ±1.2 ±2 lsb All VREF ±1.5 ±3 VCC-1.0V < VREF< VCC-0.6V ±1.0 ±2 All VREF ±1.5 ±3 guaranteed monotonic <±0.8 <±1 500ksps INL (1) Integral non-linearity 2000ksps DNL (1) Differential non-linearity Offset error -1.0 mV Temperature drift <0.01 mV/K Operating voltage drift <0.
Symbol Parameter Condition Offset error, input referred Min. 1x gain, normal mode -2.0 8x gain, normal mode -5.0 64x gain, normal mode -4.0 1x gain, normal mode Noise 1. Max. Units mV 0.5 VCC = 3.6V 8x gain, normal mode 64x gain, normal mode Note: Typ. mV rms 1.5 Ext. VREF 11 Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range. 36.4.7 DAC Characteristics Table 36-108. Power supply, reference and output range.
Table 36-110.Accuracy characteristics. Symbol RES Parameter Condition Typ. Input resolution VREF= Ext 1.0V INL (1) Integral non-linearity VREF=AVCC VREF=INT1V VREF=Ext 1.0V DNL (1) Differential non-linearity VREF=AVCC VREF=INT1V Gain error After calibration Gain calibration step size 1. Max. Units 12 Bits VCC = 1.6V ±2.0 ±3.0 VCC = 3.6V ±1.5 ±2.5 VCC = 1.6V ±2.0 ±4.0 VCC = 3.6V ±1.5 ±4.0 VCC = 1.6V ±5.0 VCC = 3.6V ±5.0 VCC = 1.6V ±1.5 3.0 VCC = 3.6V ±0.6 1.
36.4.8 Analog Comparator Characteristics Table 36-111. Analog Comparator characteristics. Symbol Voff Parameter Condition Min. Input offset voltage Ilk Input leakage current Input voltage range Typ. Max. Units <±10 mV <1 nA -0.1 AVCC V AC startup time 100 µs Vhys1 Hysteresis, none 0 mV Vhys2 Hysteresis, small Vhys3 Hysteresis, large mode = High Speed (HS) 13 mode = Low Power (LP) 30 mode = HS 30 mode = LP 60 VCC = 3.
36.4.10 Brownout Detection Characteristics Table 36-113. Brownout detection characteristics. Symbol Parameter Condition BOD level 0 falling VCC VBOT tBOD Typ. Max. 1.50 1.62 1.72 BOD level 1 falling VCC 1.8 BOD level 2 falling VCC 2.0 BOD level 3 falling VCC 2.2 BOD level 4 falling VCC 2.4 BOD level 5 falling VCC 2.6 BOD level 6 falling VCC 2.8 BOD level 7 falling VCC 3.0 Continuous mode Detection time VHYST Min. V 0.4 Sampled mode µs 1000 Hysteresis Units 1.2 % 36.4.
36.4.13 Flash and EEPROM Memory Characteristics Table 36-116. Endurance and data retention. Symbol Parameter Condition Write/Erase cycles Flash Data retention Write/Erase cycles EEPROM Data retention Min. 25°C 10K 85°C 10K 105°C 2K 25°C 100 85°C 25 105°C 10 25°C 100K 85°C 100K 105°C 30K 25°C 100 85°C 25 105°C 10 Typ. Max. Units Cycle Year Cycle Year Table 36-117. Programming time. Symbol Parameter Typ.(1) Max.
36.4.14 Clock and Oscillator Characteristics 36.4.14.1 Calibrated 32.768kHz Internal Oscillator characteristics Table 36-118. 32.768kHz internal oscillator characteristics. Symbol Parameter Condition Min. Frequency Factory calibration accuracy Typ. Max. 32.768 T = 85°C, VCC = 3.0V User calibration accuracy Units kHz -0.5 0.5 % -0.5 0.5 % Max. Units 2.2 MHz 36.4.14.2 Calibrated 2MHz RC Internal Oscillator characteristics Table 36-119. 2MHz internal oscillator characteristics.
36.4.14.5 Internal Phase Locked Loop (PLL) characteristics Table 36-122. Internal PLL characteristics. Symbo l fIN Input frequency Output frequency (1) fOUT Note: Parameter 1. Condition Min. Output frequency must be within fOUT Typ. Max. Units 0.4 64 MHz VCC= 1.6 - 1.8V 20 48 VCC= 2.7 - 3.6V 20 128 MHz Start-up time 25 µs Re-lock time 25 µs The maximum output frequency vs. supply voltage is linear between 1.8V and 2.
Table 36-124. External clock with prescaler (1)for system clock. Symbol Parameter Condition Clock Frequency (2) 1/tCK tCK Clock Period tCH Clock High Time tCL Clock Low Time tCR Rise Time (for maximum frequency) tCF Fall Time (for maximum frequency) ΔtCK Notes: Min. Typ. VCC = 1.6 - 1.8V 0 90 VCC = 2.7 - 3.6V 0 142 VCC = 1.6 - 1.8V 11 VCC = 2.7 - 3.6V 7 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 VCC = 1.6 - 1.8V 4.5 VCC = 2.7 - 3.6V 2.4 Units MHz ns ns ns VCC = 1.
Symbol Parameter Duty cycle Condition XOSCPWR=0 Min. FRQRANGE=0 40 FRQRANGE=1 42 FRQRANGE=2 or 3 45 XOSCPWR=1 2.4k 1MHz crystal, CL=20pF 8.7k 2MHz crystal, CL=20pF 2.1k 2MHz crystal 4.
36.4.14.8 External 32.768kHz crystal oscillator and TOSC characteristics Table 36-126. External 32.768kHz crystal oscillator and TOSC characteristics. Symbol Parameter Condition ESR/R1 Recommended crystal equivalent series resistance (ESR) CTOSC1 Parasitic capacitance TOSC1 pin CTOSC2 Parasitic capacitance TOSC2 pin Recommended safety factor Note: 1. Min. Typ. Max. Crystal load capacitance 6.5pF 60 Crystal load capacitance 9.0pF 35 Units 5.4 Alternate TOSC location 4.0 7.
36.4.15 SPI Characteristics Figure 36-26. SPI timing requirements in master mode. SS tMOS tSCKR tSCKF SCK (CPOL = 0) tSCKW SCK (CPOL = 1) tSCKW tMIS MISO (Data input) tMIH tSCK MSB LSB tMOH MOSI (Data output) tMOH MSB LSB Figure 36-27. SPI timing requirements in slave mode.
Table 36-127. SPI timing characteristics and requirements. Symbol Parameter Condition Min. Typ. Max. tSCK SCK Period Master (See Table 21-4 in XMEGA AU Manual) tSCKW SCK high/low width Master 0.5×SCK tSCKR SCK Rise time Master 2.7 tSCKF SCK Fall time Master 2.7 tMIS MISO setup to SCK Master 10 tMIH MISO hold after SCK Master 10 tMOS MOSI setup SCK Master 0.
36.4.16 Two-Wire Interface Characteristics Table 36-128 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel AVR XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 36-28. Figure 36-28. Two-wire interface bus timing. tof tHIGH tLOW tr SCL tSU;STA tHD;STA tHD;DAT tSU;STO tSU;DAT SDA tBUF Table 36-128. Two-wire interface characteristics. Symbol Parameter Condition Min. Typ. Max.
Symbol Parameter tHD;DAT Data hold time tSU;DAT Data setup time tSU;STO Setup time for STOP condition Bus free time between a STOP and START condition tBUF Notes: 1. 2. 3. Condition Min. Typ. Max. fSCL ≤ 100kHz 0 3.45 fSCL > 100kHz 0 0.9 fSCL ≤ 100kHz 250 fSCL > 100kHz 100 fSCL ≤ 100kHz 4.0 fSCL > 100kHz 0.6 fSCL ≤ 100kHz 4.7 fSCL > 100kHz 1.3 Units µs ns µs µs Required only for fSCL > 100kHz. Cb = Capacitance of one bus line in pF. fPER = Peripheral clock frequency.
37. Typical Characteristics 37.1 ATxmega16A4U 37.1.1 Current consumption 37.1.1.1 Active mode supply current Figure 37-1. Active supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. ICC [ µA] 600 540 3.3V 480 3.0V 420 2.7V 360 300 2.2V 240 1.8V 180 120 60 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 37-2. Active supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 12 3.3V 10 3.0V 2.7V ICC [mA] 8 6 2.2V 4 1.
Figure 37-3. Active mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 270 -40 °C 250 230 25 °C 210 85 °C 105 °C ICC [uA] 190 170 150 130 110 90 70 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-4. Active mode supply current vs. VCC. fSYS = 1MHz external clock. 800 -40 °C 25 °C 85 °C 105 °C 700 ICC [uA] 600 500 400 300 200 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
Figure 37-5. Active mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 1600 -40 °C 25 °C 85 °C 105 °C 1400 ICC [uA] 1200 1000 800 600 400 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-6. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 5900 -40 °C 25 °C 85 °C 105 °C 5400 4900 4400 ICC [uA] 3900 3400 2900 2400 1900 1400 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
Figure 37-7. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator. 5650 -40 °C 5425 5200 25 °C 4975 85 °C 105 °C ICC [uA] 4750 4525 4300 4075 3850 3625 3400 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] 37.1.1.2 Idle mode supply current Figure 37-8. Idle mode supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. I CC [µA] 140 3.3V 120 3.0V 100 2.7V 80 2.2V 60 1.8V 40 20 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.
Figure 37-9. Idle mode supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 4.5 3.3V 4.0 3.0V 3.5 2.7V I CC [mA] 3.0 2.5 2.0 2.2V 1.5 1.0 1.8V 0.5 0 0 4 8 12 16 20 24 28 32 Frequency [MHz] Figure 37-10. Idle mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 35 105 °C 34 33 -40 °C 85 °C 25 °C ICC [uA] 32 31 30 29 28 27 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
Figure 37-11. Idle mode supply current vs. VCC. fSYS = 1MHz external clock. 158 105 °C 85 °C 25 °C -40 °C 146 134 ICC [uA] 122 110 98 86 74 62 50 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-12. Idle mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 410 -40 °C 25 °C 85 °C 105 °C 385 360 ICC [uA] 335 310 285 260 235 210 185 160 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
Figure 37-13. Idle mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 2000 -40 °C 25 °C 85 °C 105 °C 1800 1600 ICC [uA] 1400 1200 1000 800 600 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-14. Idle mode current vs. VCC. fSYS = 32MHz internal oscillator. 5650 -40 °C 5425 5200 25 °C 4975 85 °C 105 °C ICC [uA] 4750 4525 4300 4075 3850 3625 3400 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.
37.1.1.3 Power-down mode supply current Figure 37-15. Power-down mode supply current vs. temperature. All functions disabled. 3.50 3.6 V 3.00 3.0 V 2.7 V 2.2 V 1.8 V 1.6 V ICC [uA] 2.50 2.00 1.50 1.00 0.50 0.00 -40 -25 -10 5 20 35 50 65 80 95 110 Temperature [°C] Figure 37-16. Power-down mode supply current vs. VCC. All functions disabled. 3.6 105 °C 3.2 2.8 ICC [uA] 2.4 2.0 1.6 1.2 85 °C 0.8 0.4 25 °C - 40 °C 0.0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
Figure 37-17. Power-down mode supply current vs. VCC. Watchdog and sampled BOD enabled. 5.1 105 °C 4.6 4.1 ICC [µA] 3.6 3.1 85 °C 2.6 2.1 1.6 25 °C -40 °C 1.1 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 37.1.1.4 Power-save mode supply current Figure 37-18. Power-save mode supply current vs.VCC. Real Time Counter enabled and running from 1.024kHz output of 32.768kHz TOSC. 0.9 Normal mode 0.8 0.7 ICC [µA] 0.6 Low-power mode 0.5 0.4 0.3 0.2 0.1 0 1.6 1.8 2.0 2.2 2.4 2.6 2.
37.1.1.5 Standby mode supply current Figure 37-19. Standby supply current vs. VCC. Standby, fSYS = 1MHz. 12.5 105 °C 11.5 10.5 9.5 85 °C ICC [uA] 8.5 25 °C -40 °C 7.5 6.5 5.5 4.5 3.5 2.5 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-20. Standby supply current vs. VCC. 25°C, running from different crystal oscillators. 480 16MHz 12MHz 440 ICC [µA] 400 360 320 8MHz 2MHz 280 240 0.454MHz 200 160 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
37.1.2 I/O Pin Characteristics 37.1.2.1 Pull-up Figure 37-21. I/O pin pull-up resistor current vs. input voltage. VCC = 1.8V. 72 64 56 48 I [µA] 40 32 24 - 40 °C 25 °C 85 °C 105 °C 16 8 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VPIN [V] Figure 37-22. I/O pin pull-up resistor current vs. input voltage. VCC = 3.0V. 120 105 90 I [µA] 75 60 45 -40 °C 25 °C 85 °C 105 °C 30 15 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.
Figure 37-23. I/O pin pull-up resistor current vs. input voltage. VCC = 3.3V. 135 120 105 90 I [µA] 75 60 45 -40 °C 25 °C 85 °C 105 °C 30 15 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 -1 0 VPIN [V] 37.1.2.2 Output Voltage vs. Sink/Source Current Figure 37-24. I/O pin output voltage vs. source current. VCC = 1.8V. 1.8 1.6 1.4 VPIN [V] 1.2 1.0 0.8 -40 °C 25 °C 0.6 0.4 105 °C 85 °C 0.2 0.
Figure 37-25. I/O pin output voltage vs. source current. VCC = 3.0V. 3.0 2.7 2.4 2.1 VPIN [V] 1.8 1.5 1.2 - 40 °C 0.9 25 °C 85 °C 0.6 105 °C 0.3 0.0 -32 -28 -24 -20 -16 -12 -8 -4 0 -12 -8 -4 0 IPIN [mA] Figure 37-26. I/O pin output voltage vs. source current. VCC = 3.3V. 3.3 3.0 2.7 VPIN [V] 2.4 2.1 1.8 -40 °C 1.5 1.2 25 °C 0.9 0.6 85 °C 0.3 105 °C 0.
Figure 37-27. I/O pin output voltage vs. source current. 4.0 3.5 3.6V 3.3V 3.0 3.0V VPIN [V] 2.7V 2.5 2.3V 2.0 1.8V 1.5 1.0 0.5 -24 -21 -18 -15 -12 -9 -6 -3 0 IPIN [mA] Figure 37-28. I/O pin output voltage vs. sink current. VCC = 1.8V. 1.0 105 °C 85 °C 0.9 0.8 0.7 25 °C VPIN [V] 0.6 -40 °C 0.5 0.4 0.3 0.2 0.1 0.
Figure 37-29. I/O pin output voltage vs. sink current. VCC = 3.0V. 0.7 0.6 105 °C 85 °C 0.5 25 °C -40 °C VPIN [V] 0.4 0.3 0.2 0.1 0.0 0 2 4 6 8 10 12 14 16 18 20 IPIN [mA] Figure 37-30. I/O pin output voltage vs. sink current. VCC = 3.3V. 1.0 105 °C 85 °C 0.9 25 °C -40 °C 0.8 0.7 VPIN [V] 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 4 8 12 16 20 24 28 32 IPIN [mA] Figure 37-31. I/O pin output voltage vs. sink current. 1.5 1.8V V PIN [V] 1.2 2.3V 2.7V 3.0V 3.3V 3.6V 0.9 0.6 0.
37.1.2.3 Thresholds and Hysteresis Figure 37-32. I/O pin input threshold voltage vs. VCC. T = 25°C. 1.8 VIH 1.6 VIL Vthreshold [V] 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Vcc [V] Figure 37-33. I/O pin input threshold voltage vs. VCC. VIH I/O pin read as “1”. 1.8 -40 °C 25 °C 85 °C 105 °C 1.7 1.6 Vthreshold [V] 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
Figure 37-34. I/O pin input threshold voltage vs. VCC. VIL I/O pin read as “0”. 1.75 -40 °C 25 °C 85 °C 105 °C 1.60 1.45 Vthreshold [V] 1.30 1.15 1.00 0.85 0.70 0.55 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 37-35. I/O pin input hysteresis vs. VCC. 0.32 0.29 0.26 Vthreshold [V] 0.23 25 °C 0.20 0.17 -40 °C 85 °C 0.14 0.11 105 °C 0.08 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
37.1.3 ADC Characteristics Figure 37-36. INL error vs. external VREF. T = 25°C, VCC = 3.6V, external reference. 1.8 1.7 1.6 Differential Signed INL [LSB] 1.5 Single-ended Unsigned 1.4 1.3 1.2 1.1 1 0.9 Single-ended Signed 0.8 0.7 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 1700 1850 3 VREF [V] Figure 37-37. INL error vs. sample rate. T = 25°C, VCC = 3.6V, VREF = 3.0V external. 1.4 1.35 1.3 Differential Mode INL [LSB] 1.25 1.2 Single-ended Unsigned 1.15 1.1 1.05 Single-ended Signed 1 0.
Figure 37-38. INL error vs. input code 2.0 1.5 INL [LSB] 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 0 512 1024 1536 2048 2560 3072 3584 4096 ADC input code Figure 37-39. DNL error vs. external VREF. T = 25°C, VCC = 3.6V, external reference. 0.9 0.88 0.86 DNL [LSB] Differential Mode 0.84 Single-ended Signed 0.82 0.8 0.78 Single-ended Unsigned 0.76 0.74 0.72 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.
Figure 37-40. DNL error vs. sample rate. T = 25°C, VCC = 3.6V, VREF = 3.0V external. 0.9 0.89 Differential Signed 0.88 DNL [LSB] 0.87 0.86 0.85 Single-ended Signed 0.84 0.83 0.82 0.81 Single-ended Unsigned 0.8 0.79 500 650 800 950 1100 1250 1400 1550 1700 1850 2000 ADC Sample Rate [kSPS] Figure 37-41. DNL error vs. input code. 0.8 0.6 DNL [LSB] 0.4 0.2 0 -0.2 -0.4 -0.
Figure 37-42. Gain error vs. VREF. T = 25°C, VCC = 3.6V, ADC sampling speed = 500ksps. 3 Single-ended Signed Gain Error [mV] 2 1 Differential Mode 0 -1 Single-ended Unsigned -2 -3 -4 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VREF [V] Figure 37-43. Gain error vs. VCC. T = 25°C, VREF = external 1.0V, ADC sampling speed = 500ksps. 2.2 1.9 Single-ended Signed Gain Error [mV] 1.6 1.3 Differential Mode 1 0.7 0.4 Single-ended Unsigned 0.1 -0.2 -0.5 1.6 1.8 2 2.2 2.4 2.6 2.
Figure 37-44. Offset error vs. VREF. T = 25°C, VCC = 3.6V, ADC sampling speed = 500ksps. -1 Offset Error [mV] -1.1 -1.2 -1.3 -1.4 -1.5 Differential Mode -1.6 -1.7 -1.8 -1.9 -2 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 VREF [V] Figure 37-45. Gain error vs. temperature. VCC = 3.0V, VREF = external 2.0V.
Figure 37-46. Offset error vs. VCC. T = 25°C, VREF = external 1.0V, ADC sampling speed = 500ksps. -0.3 -0.4 Offset Error [mV] -0.5 -0.6 -0.7 Differential Signed -0.8 -0.9 -1 -1.1 -1.2 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-47. Noise vs. VREF. T = 25°C, VCC = 3.6V, ADC sampling speed = 500ksps. 1.3 Single-ended Signed Noise [mV RMS] 1.15 Single-ended Unsigned 1 0.85 0.7 0.55 Differential Signed 0.4 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.
Figure 37-48. Noise vs. VCC. T = 25°C, VREF = external 1.0V, ADC sampling speed = 500ksps. 1.3 1.2 Single-ended Signed Noise [mV RMS] 1.1 1 0.9 0.8 Single-ended Unsigned 0.7 0.6 0.5 Differential Signed 0.4 0.3 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] 37.1.4 DAC Characteristics Figure 37-49. DAC INL error vs. VREF. VCC = 3.6V. 3.0 2.5 INL [LSB] 2.0 1.5 - 40°C 1.0 25°C 85°C 105°C 0.5 0.0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.
Figure 37-50. DNL error vs. VREF. VCC = 3.6V. 1.6 1.4 DNL[LSB] 1.2 1.0 - 40°C 0.8 25ºC 85°C 105°C 0.6 0.4 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 Vref [V] Figure 37-51. DAC noise vs. temperature. VCC = 3.0V, VREF = 2.4V . 0.185 0.180 Noise [mV RMS] 0.175 0.170 0.165 0.160 0.155 0.
37.1.5 Analog Comparator Characteristics Figure 37-52. Analog comparator hysteresis vs. VCC. High-speed, small hysteresis. 18 105 °C 85 °C -40° C 25 °C 17 16 15 14 VHYST [mV] 13 12 11 10 9 8 7 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-53. Analog comparator hysteresis vs. VCC. Low power, small hysteresis. 35 105 °C 85 °C 34 33 32 VHYST [mV] 31 25 °C 30 29 28 -40 °C 27 26 25 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
Figure 37-54. Analog comparator hysteresis vs. VCC. High-speed mode, large hysteresis. 42 105 °C 85 °C 40 38 25 °C -40 °C 36 VHYST [mV] 34 32 30 28 26 24 22 20 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-55. Analog comparator hysteresis vs. VCC. Low power, large hysteresis. 77 105 °C 74 85 °C 71 VHYST [mV] 68 65 25 °C 62 59 -40 °C 56 53 50 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
Figure 37-56. Analog comparator current source vs. calibration value. Temperature = 25°C. 7.4 ICURRENTSOURCE [µA] 6.8 6.2 5.6 5.0 4.4 3.3 V 3.0 V 2.7 V 3.8 3.2 2.2 V 1.8 V 1.6 V 2.6 2.0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CURRCALIBA[3..0] Figure 37-57. Analog comparator current source vs. calibration value. VCC = 3.0V. VCC 3.0V 7 ICURRENTSOURCE [uA] 6.5 6 5.5 5 -40 °C 25 °C 85 °C 105 °C 4.5 4 3.5 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CURRCALIBA[3..
Figure 37-58. Voltage scaler INL vs. SCALEFAC. T = 25°C, VCC = 3.0V. 0.050 0.025 INL [LSB] 0 -0.025 -0.050 -0.075 -0.100 25°C -0.125 -0.150 0 10 20 30 40 50 60 70 SCALEFAC 37.1.6 Internal 1.0V reference Characteristics Figure 37-59. ADC/DAC Internal 1.0V reference Calibratedvs. at Ttemperature. 85 C 1.004 1.6 V 1.8 V 2.2 V 2.7 V 3.0 V 3.6 V 1.002 Bandgap Voltage [V] 1.000 0.998 0.996 0.994 0.992 0.990 0.988 0.
37.1.7 BOD Characteristics Figure 37-60. BOD thresholds vs. temperature. BOD level = 1.6V. 1.635 Rising Vcc 1.630 VBOT [V] 1.625 Falling Vcc 1.620 1.615 1.610 1.605 1.600 -40 -25 -10 5 20 35 50 65 80 95 110 Temperature [°C] Figure 37-61. BOD thresholds vs. temperature. BOD level = 3.0V. 3.06 Rising Vcc 3.05 3.04 VBOT [V] 3.03 3.02 3.01 Falling Vcc 3.00 2.99 2.98 2.
37.1.8 External Reset Characteristics Figure 37-62. Minimum Reset pin pulse width vs. VCC. 130 125 120 115 tRST [ns] 110 105 100 105 °C 85 °C 95 90 25 °C -40 °C 85 80 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 37-63. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 1.8V. 72 64 56 IRESET [uA] 48 40 32 24 -40 °C 25 °C 85 °C 105 °C 16 8 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.
Figure 37-64. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.0V. 120 105 90 IRESET [µA] 75 60 45 -40 °C 25 °C 85 °C 105 °C 30 15 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 VRESET [V] Figure 37-65. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.3V. 140 120 IRESET [uA] 100 80 60 40 -40 °C 25 °C 85 °C 105 °C 20 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.
Figure 37-66. Reset pin input threshold voltage vs. VCC. VIH - Reset pin read as “1”. 2.20 -40 °C 25 °C 85 °C 105 °C 2.05 Vthreshold [V] 1.90 1.75 1.60 1.45 1.30 1.15 1.00 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 37-67. Reset pin input threshold voltage vs. VCC. VIL - Reset pin read as “0”. 1.75 -40 °C 25 °C 85 °C 105 °C 1.60 1.45 Vthreshold [V] 1.30 1.15 1.00 0.85 0.70 0.55 0.40 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
37.1.9 Power-on Reset Characteristics Figure 37-68. Power-on reset current consumption vs. VCC. BOD level = 3.0V, enabled in continuous mode. ICC [µA] 700 -40 °C 600 25 °C 500 85 °C 105 °C 400 300 200 100 0 0.4 0.7 1.0 1.3 1.6 1.9 2.2 2.5 2.8 VCC [V] Figure 37-69. Power-on reset current consumption vs. VCC. BOD level = 3.0V, enabled in sampled mode. 650 -40 °C 585 520 25 °C ICC [µA] 455 85 ° °C 105°°C 390 325 260 195 130 65 0 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.
37.1.10 Oscillator Characteristics 37.1.10.1 Ultra Low-Power internal oscillator Figure 37-70. Ultra Low-Power internal oscillator frequency vs. temperature. 32.8 32.4 Frequency [kHz] 32.0 31.6 31.2 30.8 3.6 V 3.0 V 2.7 V 2.2 V 1.8 V 1.6 V 30.4 30.0 29.6 -40 -25 -10 5 20 35 50 65 80 95 110 Temperature [°C] 37.1.10.2 32.768kHz Internal Oscillator Figure 37-71. 32.768kHz internal oscillator frequency vs. temperature. 32.875 3.6 V 3.0 V 2.2 V 2.7 V 1.8 V 1.6 V 32.850 Frequency [kHz] 32.
Figure 37-72. 32.768kHz internal oscillator frequency vs. calibration value. VCC = 3.0V, T = 25°C. 55 Frequency [kHz] 50 45 40 35 30 25 20 0 26 52 78 104 130 156 182 208 234 260 RC32KCAL[7..0] 37.1.10.3 2MHz Internal Oscillator Figure 37-73. 2MHz internal oscillator frequency vs. temperature. DFLL disabled. 2.16 2.14 Frequency [MHz] 2.12 2.10 2.08 2.06 2.04 3.6 V 3.0 V 2.7 V 2.2 V 1.8 V 1.6 V 2.02 2.00 1.98 1.
Figure 37-74. 2MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator . 2.0085 2.0070 3.6 V 1.6 V 2.2 V 1.8 V 3.0 V 2.7 V Frequency [MHz] 2.0055 2.0040 2.0025 2.0010 1.9995 1.9980 1.9965 1.9950 -40 -25 -10 5 20 35 50 65 80 95 110 Temperature [°C] Figure 37-75. 2MHz internal oscillator CALA calibration step size. VCC = 3V. 0.31 % Frequency Step size [%] 0.29 % 0.27 % 0.25 % 0.23 % 0.21 % -40 °C 0.19 % 25 °C 85 °C 105 °C 0.17 % 0.
37.1.10.4 32MHz Internal Oscillator Figure 37-76. 32MHz internal oscillator frequency vs. temperature. DFLL disabled. 36.0 35.5 Frequency [MHz] 35.0 34.5 34.0 33.5 33.0 3.6 V 3.0 V 2.7 V 2.2 V 1.8 V 1.6 V 32.5 32.0 31.5 31.0 -40 -25 -10 5 20 35 50 65 80 95 110 Temperature [°C] Figure 37-77. 32MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 32.145 3.6 V 1.61.6 V V 1.8 V 2.2 V 2.7 V 3.0 V 32.120 Frequency [MHz] 32.095 32.070 32.
Figure 37-78. 32MHz internal oscillator CALA calibration step size. VCC = 3.0V. 0.38 % Frequency Step size [%] 0.34 % 0.30 % 0.26 % 0.22 % 85°C 105°C 25°C - 40°C 0.18 % 0.14 % 0.10 % 0 16 32 48 64 80 96 112 128 CALA Figure 37-79. 32MHz internal oscillator frequency vs. CALB calibration value. VCC = 3.0V.
37.1.10.5 32MHz internal oscillator calibrated to 48MHz Figure 37-80. 48MHz internal oscillator frequency vs. temperature. DFLL disabled. 54 53 Frequency [MHz] 52 51 50 3.6 V 3.0 V 2.7 V 2.2 V 1.8 V 1.6 V 49 48 47 46 -40 -25 -10 5 20 35 50 65 80 95 110 Temperature [°C] Figure 37-81. 48MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 48.25 3.6 V 1.6 V 1.8 V 2.7 V 2.2 V 48.20 Frequency [MHz] 48.15 48.10 3.0 V 48.05 48.00 47.95 47.
Figure 37-82. 48MHz internal oscillator CALA calibration step size. VCC = 3.0V. V 3.0 V CC 0.34 % Frequency Step size [%] 0.31 % 0.28 % 0.25 % 0.22 % 0.19 % -40 °C 25 °C 0.16 % 85 °C 105 °C 0.13 % 0.10 % 0 16 32 48 64 80 96 112 128 CALA 37.1.11 Two-Wire Interface characteristics Figure 37-83. SDA hold time vs. supply voltage. 300 295 290 Holdtime [ns] 285 105°C 280 85°C 275 270 25°C 265 - 40°C 260 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.
37.1.12 PDI characteristics Figure 37-84. Maximum PDI frequency vs. VCC. 34 25 °C 105 °C -40 °C 85 °C 31 28 f MAX [MHz] 25 22 19 16 13 10 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
37.2 ATxmega32A4U 37.2.1 Current consumption 37.2.1.1 Active mode supply current Figure 37-85.Active supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. ICC [ µA] 600 540 3.3V 480 3.0V 420 2.7V 360 300 2.2V 240 1.8V 180 120 60 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 37-86.Active supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 12 3.3V 10 3.0V 2.7V ICC [mA] 8 6 2.2V 4 1.
Figure 37-87.Active mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 270 -40 °C 250 230 25 °C 210 85 °C 105 °C ICC [uA] 190 170 150 130 110 90 70 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-88.Active mode supply current vs. VCC. fSYS = 1MHz external clock. 800 -40 °C 25 °C 85 °C 105 °C 700 ICC [uA] 600 500 400 300 200 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
Figure 37-89.Active mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 1600 -40 °C 25 °C 85 °C 105 °C 1400 ICC [uA] 1200 1000 800 600 400 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-90.Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 5900 -40 °C 25 °C 85 °C 105 °C 5400 4900 4400 ICC [uA] 3900 3400 2900 2400 1900 1400 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
Figure 37-91.Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator. 5650 -40 °C 5425 5200 25 °C 4975 85 °C 105 °C ICC [uA] 4750 4525 4300 4075 3850 3625 3400 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] 37.2.1.2 Idle mode supply current Figure 37-92.Idle mode supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. I CC [µA] 140 3.3V 120 3.0V 100 2.7V 80 2.2V 60 1.8V 40 20 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.
Figure 37-93.Idle mode supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 4.5 3.3V 4.0 3.0V 3.5 2.7V I CC [mA] 3.0 2.5 2.0 2.2V 1.5 1.0 1.8V 0.5 0 0 4 8 12 16 20 24 28 32 Frequency [MHz] Figure 37-94. Idle mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 35 105 °C 34 33 -40 °C 85 °C 25 °C ICC [uA] 32 31 30 29 28 27 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
Figure 37-95. Idle mode supply current vs. VCC. fSYS = 1MHz external clock. 158 105 °C 85 °C 25 °C -40 °C 146 134 ICC [uA] 122 110 98 86 74 62 50 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-96. Idle mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 410 -40 °C 25 °C 85 °C 105 °C 385 360 ICC [uA] 335 310 285 260 235 210 185 160 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
Figure 37-97. Idle mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 2000 -40 °C 25 °C 85 °C 105 °C 1800 1600 ICC [uA] 1400 1200 1000 800 600 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-98. Idle mode current vs. VCC. fSYS = 32MHz internal oscillator. 5650 -40 °C 5425 5200 25 °C 4975 85 °C 105 °C ICC [uA] 4750 4525 4300 4075 3850 3625 3400 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.
37.2.1.3 Power-down mode supply current Figure 37-99. Power-down mode supply current vs. temperature. All functions disabled. 3.50 3.6 V 3.00 3.0 V 2.7 V 2.2 V 1.8 V 1.6 V ICC [uA] 2.50 2.00 1.50 1.00 0.50 0.00 -40 -25 -10 5 20 35 50 65 80 95 110 Temperature [°C] Figure 37-100. Power-down mode supply current vs. VCC. All functions disabled. 3.6 105 °C 3.2 2.8 ICC [uA] 2.4 2.0 1.6 1.2 85 °C 0.8 0.4 25 °C - 40 °C 0.0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
Figure 37-101. Power-down mode supply current vs. VCC. Watchdog and sampled BOD enabled. 5.1 105 °C 4.6 4.1 ICC [µA] 3.6 3.1 85 °C 2.6 2.1 1.6 25 °C -40 °C 1.1 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 37.2.1.4 Power-save mode supply current Figure 37-102. Power-save mode supply current vs.VCC. Real Time Counter enabled and running from 1.024kHz output of 32.768kHz TOSC. 0.9 Normal mode 0.8 0.7 ICC [µA] 0.6 Low-power mode 0.5 0.4 0.3 0.2 0.1 0 1.6 1.8 2.0 2.2 2.4 2.
37.2.1.5 Standby mode supply current Figure 37-103. Standby supply current vs. VCC. Standby, fSYS = 1MHz. 12.5 105 °C 11.5 10.5 9.5 85 °C ICC [uA] 8.5 25 °C -40 °C 7.5 6.5 5.5 4.5 3.5 2.5 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-104. Standby supply current vs. VCC. 25°C, running from different crystal oscillators. 480 16MHz 12MHz 440 ICC [µA] 400 360 320 8MHz 2MHz 280 240 0.454MHz 200 160 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
37.2.2 I/O Pin Characteristics 37.2.2.1 Pull-up Figure 37-105. I/O pin pull-up resistor current vs. input voltage. VCC = 1.8V. 72 64 56 48 I [µA] 40 32 24 - 40 °C 25 °C 85 °C 105 °C 16 8 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VPIN [V] Figure 37-106. I/O pin pull-up resistor current vs. input voltage. VCC = 3.0V. 120 105 90 I [µA] 75 60 45 -40 °C 25 °C 85 °C 105 °C 30 15 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.
Figure 37-107. I/O pin pull-up resistor current vs. input voltage. VCC = 3.3V. 135 120 105 90 I [µA] 75 60 45 -40 °C 25 °C 85 °C 105 °C 30 15 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 -1 0 VPIN [V] 37.2.2.2 Output Voltage vs. Sink/Source Current Figure 37-108. I/O pin output voltage vs. source current. VCC = 1.8V. 1.8 1.6 1.4 VPIN [V] 1.2 1.0 0.8 -40 °C 25 °C 0.6 0.4 105 °C 85 °C 0.2 0.
Figure 37-109. I/O pin output voltage vs. source current. VCC = 3.0V. 3.0 2.7 2.4 2.1 VPIN [V] 1.8 1.5 1.2 - 40 °C 0.9 25 °C 85 °C 0.6 105 °C 0.3 0.0 -32 -28 -24 -20 -16 -12 -8 -4 0 -12 -8 -4 0 IPIN [mA] Figure 37-110. I/O pin output voltage vs. source current. VCC = 3.3V. 3.3 3.0 2.7 VPIN [V] 2.4 2.1 1.8 -40 °C 1.5 1.2 25 °C 0.9 0.6 85 °C 0.3 105 °C 0.
Figure 37-111. I/O pin output voltage vs. source current. 4.0 3.5 3.6V 3.3V 3.0 3.0V VPIN [V] 2.7V 2.5 2.3V 2.0 1.8V 1.5 1.0 0.5 -24 -21 -18 -15 -12 -9 -6 -3 0 IPIN [mA] Figure 37-112. I/O pin output voltage vs. sink current. VCC = 1.8V. 1.0 105 °C 85 °C 0.9 0.8 0.7 25 °C VPIN [V] 0.6 -40 °C 0.5 0.4 0.3 0.2 0.1 0.
Figure 37-113. I/O pin output voltage vs. sink current. VCC = 3.0V. 0.7 0.6 105 °C 85 °C 0.5 25 °C -40 °C VPIN [V] 0.4 0.3 0.2 0.1 0.0 0 2 4 6 8 10 12 14 16 18 20 IPIN [mA] Figure 37-114. I/O pin output voltage vs. sink current. VCC = 3.3V. 1.0 105 °C 85 °C 0.9 25 °C -40 °C 0.8 0.7 VPIN [V] 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 4 8 12 16 20 24 28 32 IPIN [mA] Figure 37-115. I/O pin output voltage vs. sink current. 1.5 1.8V V PIN [V] 1.2 2.3V 2.7V 3.0V 3.3V 3.6V 0.9 0.6 0.
37.2.2.3 Thresholds and Hysteresis Figure 37-116. I/O pin input threshold voltage vs. VCC. T = 25°C. 1.8 VIH 1.6 VIL Vthreshold [V] 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Vcc [V] Figure 37-117. I/O pin input threshold voltage vs. VCC. VIH I/O pin read as “1”. 1.8 -40 °C 25 °C 85 °C 105 °C 1.7 1.6 Vthreshold [V] 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
Figure 37-118. I/O pin input threshold voltage vs. VCC. VIL I/O pin read as “0”. 1.75 -40 °C 25 °C 85 °C 105 °C 1.60 1.45 Vthreshold [V] 1.30 1.15 1.00 0.85 0.70 0.55 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 37-119. I/O pin input hysteresis vs. VCC. 0.32 0.29 0.26 Vthreshold [V] 0.23 25 °C 0.20 0.17 -40 °C 85 °C 0.14 0.11 105 °C 0.08 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
37.2.3 ADC Characteristics Figure 37-120. INL error vs. external VREF. T = 25°C, VCC = 3.6V, external reference. 1.8 1.7 1.6 Differential Signed INL [LSB] 1.5 Single-ended Unsigned 1.4 1.3 1.2 1.1 1 0.9 Single-ended Signed 0.8 0.7 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 1700 1850 3 VREF [V] Figure 37-121. INL error vs. sample rate. T = 25°C, VCC = 3.6V, VREF = 3.0V external. 1.4 1.35 1.3 Differential Mode INL [LSB] 1.25 1.2 Single-ended Unsigned 1.15 1.1 1.
Figure 37-122. INL error vs. input code 2.0 1.5 INL [LSB] 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 0 512 1024 1536 2048 2560 3072 3584 4096 ADC input code Figure 37-123. DNL error vs. external VREF. T = 25°C, VCC = 3.6V, external reference. 0.9 0.88 0.86 DNL [LSB] Differential Mode 0.84 Single-ended Signed 0.82 0.8 0.78 Single-ended Unsigned 0.76 0.74 0.72 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.
Figure 37-124. DNL error vs. sample rate. T = 25°C, VCC = 3.6V, VREF = 3.0V external. 0.9 0.89 Differential Signed 0.88 DNL [LSB] 0.87 0.86 0.85 Single-ended Signed 0.84 0.83 0.82 0.81 Single-ended Unsigned 0.8 0.79 500 650 800 950 1100 1250 1400 1550 1700 1850 2000 ADC Sample Rate [kSPS] Figure 37-125. DNL error vs. input code. 0.8 0.6 DNL [LSB] 0.4 0.2 0 -0.2 -0.4 -0.
Figure 37-126. Gain error vs. VREF. T = 25°C, VCC = 3.6V, ADC sampling speed = 500ksps. 3 Single-ended Signed Gain Error [mV] 2 1 Differential Mode 0 -1 Single-ended Unsigned -2 -3 -4 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VREF [V] Figure 37-127. Gain error vs. VCC. T = 25°C, VREF = external 1.0V, ADC sampling speed = 500ksps. 2.2 1.9 Single-ended Signed Gain Error [mV] 1.6 1.3 Differential Mode 1 0.7 0.4 Single-ended Unsigned 0.1 -0.2 -0.5 1.6 1.8 2 2.2 2.4 2.
Figure 37-128. Offset error vs. VREF. T = 25°C, VCC = 3.6V, ADC sampling speed = 500ksps. -1 Offset Error [mV] -1.1 -1.2 -1.3 -1.4 -1.5 Differential Mode -1.6 -1.7 -1.8 -1.9 -2 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 VREF [V] Figure 37-129. Gain error vs. temperature. VCC = 3.0V, VREF = external 2.0V.
Figure 37-130. Offset error vs. VCC. T = 25°C, VREF = external 1.0V, ADC sampling speed = 500ksps. -0.3 -0.4 Offset Error [mV] -0.5 -0.6 -0.7 Differential Signed -0.8 -0.9 -1 -1.1 -1.2 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-131. Noise vs. VREF. T = 25°C, VCC = 3.6V, ADC sampling speed = 500ksps. 1.3 Single-ended Signed Noise [mV RMS] 1.15 Single-ended Unsigned 1 0.85 0.7 0.55 Differential Signed 0.4 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.
Figure 37-132. Noise vs. VCC. T = 25°C, VREF = external 1.0V, ADC sampling speed = 500ksps. 1.3 1.2 Single-ended Signed Noise [mV RMS] 1.1 1 0.9 0.8 Single-ended Unsigned 0.7 0.6 0.5 Differential Signed 0.4 0.3 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] 37.2.4 DAC Characteristics Figure 37-133. DAC INL error vs. VREF. VCC = 3.6V. 3.0 2.5 INL [LSB] 2.0 1.5 - 40°C 1.0 25°C 85°C 105°C 0.5 0.0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.
Figure 37-134. DNL error vs. VREF. VCC = 3.6V. 1.6 1.4 DNL[LSB] 1.2 1.0 - 40°C 0.8 25ºC 85°C 105°C 0.6 0.4 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 Vref [V] Figure 37-135. DAC noise vs. temperature. VCC = 3.0V, VREF = 2.4V . 0.185 0.180 Noise [mV RMS] 0.175 0.170 0.165 0.160 0.155 0.
37.2.5 Analog Comparator Characteristics Figure 37-136. Analog comparator hysteresis vs. VCC. High-speed, small hysteresis. 18 105 °C 85 °C -40° C 25 °C 17 16 15 14 VHYST [mV] 13 12 11 10 9 8 7 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-137. Analog comparator hysteresis vs. VCC. Low power, small hysteresis. 35 105 °C 85 °C 34 33 32 VHYST [mV] 31 25 °C 30 29 28 -40 °C 27 26 25 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
Figure 37-138. Analog comparator hysteresis vs. VCC. High-speed mode, large hysteresis. 42 105 °C 85 °C 40 38 25 °C -40 °C 36 VHYST [mV] 34 32 30 28 26 24 22 20 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-139. Analog comparator hysteresis vs. VCC. Low power, large hysteresis. 77 105 °C 74 85 °C 71 VHYST [mV] 68 65 25 °C 62 59 -40 °C 56 53 50 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
Figure 37-140. Analog comparator current source vs. calibration value. Temperature = 25°C. 7.4 ICURRENTSOURCE [µA] 6.8 6.2 5.6 5.0 4.4 3.3 V 3.0 V 2.7 V 3.8 3.2 2.2 V 1.8 V 1.6 V 2.6 2.0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CURRCALIBA[3..0] Figure 37-141. Analog comparator current source vs. calibration value. VCC = 3.0V. VCC 3.0V 7 ICURRENTSOURCE [uA] 6.5 6 5.5 5 -40 °C 25 °C 85 °C 105 °C 4.5 4 3.5 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CURRCALIBA[3..
Figure 37-142. Voltage scaler INL vs. SCALEFAC. T = 25°C, VCC = 3.0V. 0.050 0.025 INL [LSB] 0 -0.025 -0.050 -0.075 -0.100 25°C -0.125 -0.150 0 10 20 30 40 50 60 70 SCALEFAC 37.2.6 Internal 1.0V reference Characteristics Figure 37-143. ADC/DAC Internal 1.0V reference vs.T temperature. Calibrated at 85 C 1.004 1.6 V 1.8 V 2.2 V 2.7 V 3.0 V 3.6 V 1.002 Bandgap Voltage [V] 1.000 0.998 0.996 0.994 0.992 0.990 0.988 0.
37.2.7 BOD Characteristics Figure 37-144. BOD thresholds vs. temperature. BOD level = 1.6V. 1.635 Rising Vcc 1.630 VBOT [V] 1.625 Falling Vcc 1.620 1.615 1.610 1.605 1.600 -40 -25 -10 5 20 35 50 65 80 95 110 Temperature [°C] Figure 37-145. BOD thresholds vs. temperature. BOD level = 3.0V. 3.06 Rising Vcc 3.05 3.04 VBOT [V] 3.03 3.02 3.01 Falling Vcc 3.00 2.99 2.98 2.
37.2.8 External Reset Characteristics Figure 37-146. Minimum Reset pin pulse width vs. VCC. 130 125 120 115 tRST [ns] 110 105 100 105 °C 85 °C 95 90 25 °C -40 °C 85 80 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 37-147. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 1.8V. 72 64 56 IRESET [uA] 48 40 32 24 -40 °C 25 °C 85 °C 105 °C 16 8 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.
Figure 37-148. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.0V. 120 105 90 IRESET [µA] 75 60 45 -40 °C 25 °C 85 °C 105 °C 30 15 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 VRESET [V] Figure 37-149. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.3V. 140 120 IRESET [uA] 100 80 60 40 -40 °C 25 °C 85 °C 105 °C 20 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.
Figure 37-150. Reset pin input threshold voltage vs. VCC. VIH - Reset pin read as “1”. 2.20 -40 °C 25 °C 85 °C 105 °C 2.05 Vthreshold [V] 1.90 1.75 1.60 1.45 1.30 1.15 1.00 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 37-151. Reset pin input threshold voltage vs. VCC. VIL - Reset pin read as “0”. 1.75 -40 °C 25 °C 85 °C 105 °C 1.60 1.45 Vthreshold [V] 1.30 1.15 1.00 0.85 0.70 0.55 0.40 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
37.2.9 Power-on Reset Characteristics Figure 37-152. Power-on reset current consumption vs. VCC. BOD level = 3.0V, enabled in continuous mode. ICC [µA] 700 -40 °C 600 25 °C 500 85 °C 105 °C 400 300 200 100 0 0.4 0.7 1.0 1.3 1.6 1.9 2.2 2.5 2.8 VCC [V] Figure 37-153. Power-on reset current consumption vs. VCC. BOD level = 3.0V, enabled in sampled mode. 650 -40 °C 585 520 25 °C ICC [µA] 455 85 ° °C 105°°C 390 325 260 195 130 65 0 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.
37.2.10 Oscillator Characteristics 37.2.10.1 Ultra Low-Power internal oscillator Figure 37-154. Ultra Low-Power internal oscillator frequency vs. temperature. 32.8 32.4 Frequency [kHz] 32.0 31.6 31.2 30.8 3.6 V 3.0 V 2.7 V 2.2 V 1.8 V 1.6 V 30.4 30.0 29.6 -40 -25 -10 5 20 35 50 65 80 95 110 Temperature [°C] 37.2.10.2 32.768kHz Internal Oscillator Figure 37-155. 32.768kHz internal oscillator frequency vs. temperature. 32.875 3.6 V 3.0 V 2.2 V 2.7 V 1.8 V 1.6 V 32.850 Frequency [kHz] 32.
Figure 37-156. 32.768kHz internal oscillator frequency vs. calibration value. VCC = 3.0V, T = 25°C. 55 Frequency [kHz] 50 45 40 35 30 25 20 0 26 52 78 104 130 156 182 208 234 260 RC32KCAL[7..0] 37.2.10.3 2MHz Internal Oscillator Figure 37-157. 2MHz internal oscillator frequency vs. temperature. DFLL disabled. 2.16 2.14 Frequency [MHz] 2.12 2.10 2.08 2.06 2.04 3.6 V 3.0 V 2.7 V 2.2 V 1.8 V 1.6 V 2.02 2.00 1.98 1.
Figure 37-158. 2MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator . 2.0085 2.0070 3.6 V 1.6 V 2.2 V 1.8 V 3.0 V 2.7 V Frequency [MHz] 2.0055 2.0040 2.0025 2.0010 1.9995 1.9980 1.9965 1.9950 -40 -25 -10 5 20 35 50 65 80 95 110 Temperature [°C] Figure 37-159. 2MHz internal oscillator CALA calibration step size. VCC = 3V. 0.31 % Frequency Step size [%] 0.29 % 0.27 % 0.25 % 0.23 % 0.21 % -40 °C 0.19 % 25 °C 85 °C 105 °C 0.17 % 0.
37.2.10.4 32MHz Internal Oscillator Figure 37-160. 32MHz internal oscillator frequency vs. temperature. DFLL disabled. 36.0 35.5 Frequency [MHz] 35.0 34.5 34.0 33.5 33.0 3.6 V 3.0 V 2.7 V 2.2 V 1.8 V 1.6 V 32.5 32.0 31.5 31.0 -40 -25 -10 5 20 35 50 65 80 95 110 Temperature [°C] Figure 37-161. 32MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 32.145 3.6 V 1.61.6 V V 1.8 V 2.2 V 2.7 V 3.0 V 32.120 Frequency [MHz] 32.095 32.070 32.
Figure 37-162. 32MHz internal oscillator CALA calibration step size. VCC = 3.0V. 0.38 % Frequency Step size [%] 0.34 % 0.30 % 0.26 % 0.22 % 85°C 105°C 25°C - 40°C 0.18 % 0.14 % 0.10 % 0 16 32 48 64 80 96 112 128 CALA Figure 37-163. 32MHz internal oscillator frequency vs. CALB calibration value. VCC = 3.0V.
37.2.10.5 32MHz internal oscillator calibrated to 48MHz Figure 37-164. 48MHz internal oscillator frequency vs. temperature. DFLL disabled. 54 53 Frequency [MHz] 52 51 50 3.6 V 3.0 V 2.7 V 2.2 V 1.8 V 1.6 V 49 48 47 46 -40 -25 -10 5 20 35 50 65 80 95 110 Temperature [°C] Figure 37-165. 48MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 48.25 3.6 V 1.6 V 1.8 V 2.7 V 2.2 V 48.20 Frequency [MHz] 48.15 48.10 3.0 V 48.05 48.00 47.95 47.
Figure 37-166. 48MHz internal oscillator CALA calibration step size. VCC = 3.0V. 0.34 % Frequency Step size [%] 0.31 % 0.28 % 0.25 % 0.22 % 0.19 % -40 °C 25 °C 0.16 % 85 °C 105 °C 0.13 % 0.10 % 0 16 32 48 64 80 96 112 128 CALA 37.2.11 Two-Wire Interface characteristics Figure 37-167. SDA hold time vs. supply voltage. 300 295 290 Holdtime [ns] 285 105°C 280 85°C 275 270 25°C 265 - 40°C 260 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.
37.2.12 PDI characteristics Figure 37-168. Maximum PDI frequency vs. VCC. 34 25 °C 105 °C -40 °C 85 °C 31 28 f MAX [MHz] 25 22 19 16 13 10 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
37.3 ATxmega64A4U 37.3.1 Current consumption 37.3.1.1 Active mode supply current Figure 37-169. Active supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. 700 3.6V 600 ICC [µA] 500 3.0V 400 2.7V 300 2.2V 200 1.8V 1.6V 100 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 37-170. Active supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 12 3.6V 10 3.0V ICC [mA] 8 2.7V 6 4 2.2V 2 1.8V 1.
Figure 37-171. Active mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 250 - 40°C ICC [µA] 230 210 25°C 190 85°C 105°C 170 150 130 110 90 70 50 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 37-172. Active mode supply current vs. VCC. fSYS = 1MHz external clock. 680 - 40°C 25°C 85°C 105°C 630 580 530 ICC [µA] 480 430 380 330 280 230 180 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
Figure 37-173. Active mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 1300 - 40°C 25°C 85°C 105°C 1200 1100 ICC [µA] 1000 900 800 700 600 500 400 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 37-174. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 4.8 - 40°C 25°C 85°C 105°C 4.4 4.0 ICC [mA] 3.6 3.2 2.8 2.4 2.0 1.6 1.2 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
Figure 37-175. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator. 12.0 - 40°C 11.5 25°C 85°C 105°C 11.0 ICC [mA] 10.5 10.0 9.5 9.0 8.5 8.0 7.5 7.0 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] 37.3.1.2 Idle mode supply current Figure 37-176. Idle mode supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. 150 3.6 V 135 ICC [µA] 120 105 3.0 V 90 2.7 V 75 2.2 V 60 1.8 V 1.6 V 45 30 15 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 37-177. Idle mode supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 4.5 3.6 V ICC [mA] 4.0 3.5 3.0 V 3.0 2.7 V 2.5 2.0 2.2 V 1.5 1.0 1.8 V 1.6 V 0.5 0.0 0 4 8 12 16 F 20 24 28 32 [MH ] Figure 37-178. Idle mode supply current vs. VCC. fSYS = 32.768kHz internal . Internal Oscillator fSYSoscillator 32.768kHz 34.75 105°C - 40°C 34.00 33.25 85°C 25°C ICC [µA] 32.50 31.75 31.00 30.25 29.50 28.75 28.00 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
Figure 37-179. Idle mode supply current vs. VCC. fSYS = 1MHz external clock. 153 105°C 85°C 25°C - 40°C 141 129 ICC [µA] 117 105 93 81 69 57 45 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 37-180. Idle mode supply current vs. VCC. fSYS = 2MHz internal oscillator. 400 - 40°C 25°C 85°C 105°C 375 350 325 ICC [µA] 300 275 250 225 200 175 150 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
Figure 37-181. Idle mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 1850 - 40°C 25°C 85°C 105°C 1700 1550 ICC [µA] 1400 1250 1100 950 800 650 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 37-182. Idle mode current vs. VCC. fSYS = 32MHz internal oscillator. 5.1 4.9 - 40°C 4.7 25°C 85°C 105°C ICC [mA] 4.5 4.3 4.1 3.9 3.7 3.5 3.3 3.1 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.
37.3.1.3 Power-down mode supply current Figure 37-183. Power-down mode supply current vs. temperature. All functions disabled. 2.7 3.6 V 2.4 3.0 V 2.7 V 2.2 V 1.8 V 1.6 V 2.1 ICC [µA] 1.8 1.5 1.2 0.9 0.6 0.3 0.0 -45 -30 -15 0 15 30 45 60 75 90 105 Temperature [°C] Figure 37-184. Power-down mode supply current vs. VCC. All functions disabled. 2.7 105°C 2.4 2.1 ICC [µA] 1.8 1.5 1.2 0.9 85°C 0.6 0.3 25°C - 40°C 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
Figure 37-185. Power-down mode supply current vs. VCC. Watchdog and sampled BOD enabled. 4.10 105°C 3.80 3.50 3.20 ICC [µA] 2.90 2.60 2.30 85°C 2.00 1.70 25°C - 40°C 1.40 1.10 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 37.3.1.4 Power-save mode supply current Figure 37-186. Power-save mode supply current vs.VCC. Real Time Counter enabled and running from 1.024kHz output of 32.768kHz TOSC. 0.9 Normal mode 0.8 0.7 ICC [µA] 0.6 Low-power mode 0.5 0.4 0.3 0.2 0.1 0 1.6 1.8 2.
37.3.1.5 Standby mode supply current Figure 37-187. Standby supply current vs. VCC. Standby, fSYS = 1MHz. 12.5 105 °C 11.5 10.5 9.5 85 °C ICC [uA] 8.5 25 °C -40 °C 7.5 6.5 5.5 4.5 3.5 2.5 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-188. Standby supply current vs. VCC. 25°C, running from different crystal oscillators. 480 16MHz 12MHz 440 ICC [µA] 400 360 320 8MHz 2MHz 280 240 0.454MHz 200 160 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
37.3.2 I/O Pin Characteristics 37.3.2.1 Pull-up Figure 37-189. I/O pin pull-up resistor current vs. input voltage. VCC = 1.8V. 70 60 IPIN [uA] 50 40 30 20 - 40°C 25°C 85°C 105°C 10 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VPIN [V] Figure 37-190. I/O pin pull-up resistor current vs. input voltage. VCC = 3.0V. 120 105 90 IPIN [µA] 75 60 45 30 - 40°C 25°C 85°C 105°C 15 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.
Figure 37-191. I/O pin pull-up resistor current vs. input voltage. VCC = 3.3V. 135 120 105 IPIN [µA] 90 75 60 45 - 40°C 25°C 85°C 105°C 30 15 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 VPIN [V] 37.3.2.2 Output Voltage vs. Sink/Source Current Figure 37-192. I/O pin output voltage vs. source current. VCC = 1.8V. 1.9 1.7 VPIN [V] 1.5 1.3 - 40°C 1.1 25°C 0.9 105°C 85°C 0.7 0.
Figure 37-193. I/O pin output voltage vs. source current. VCC = 3.0V. 3.2 2.8 2.4 VPIN [V] 2.0 1.6 - 40°C 1.2 25°C 0.8 85°C 105°C 0.4 0.0 -30 -27 -24 -21 -18 -15 -12 -9 -6 -3 0 -9 -6 -3 0 IPIN [mA] Figure 37-194. I/O pin output voltage vs. source current. VCC = 3.3V. 3.6 3.2 2.8 VPIN [V] 2.4 - 40°C 2.0 1.6 25°C 1.2 105°C 0.8 85°C 0.4 0.
Figure 37-195. I/O pin output voltage vs. source current. 3.7 3.6 V 3.3 V 3.3 3.0 V 2.9 VPIN [V] 2.7 V 2.5 2.1 1.8 V 1.6 V 1.7 1.3 0.9 0.5 -24 -21 -18 -15 -12 -9 -6 -3 0 IPIN [mA] Figure 37-196. I/O pin output voltage vs. sink current. VCC = 1.8V. 1.0 85°C 0.9 0.8 25°C 0.7 105°C VPIN [V] 0.6 - 40°C 0.5 0.4 0.3 0.2 0.1 0.
Figure 37-197. I/O pin output voltage vs. sink current. VCC = 3.0V. 1.0 105°C 85°C 0.9 25°C 0.8 - 40°C 0.7 VPIN [V] 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 3 6 9 12 15 18 21 24 27 30 IPIN [mA] Figure 37-198. I/O pin output voltage vs. sink current. VCC = 3.3V. 1.0 105°C 85°C 0.9 0.8 25°C - 40°C 0.7 VPIN [V] 0.6 0.5 0.4 0.3 0.2 0.1 0.
Figure 37-199. I/O pin output voltage vs. sink current. 1.50 1.6 V 1.35 1.8 V 1.20 VPIN [V] 1.05 2.7 V 3.0 V 3.3 V 3.6 V 0.90 0.75 0.60 0.45 0.30 0.15 0.00 0 3 6 9 12 15 18 21 24 27 30 IPIN [mA] 37.3.2.3 Thresholds and Hysteresis Figure 37-200. I/O pin input threshold voltage vs. VCC. T = 25°C. 1.8 VIH 1.6 VIL Vthreshold [V] 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
Figure 37-201. I/O pin input threshold voltage vs. VCC. VIH I/O pin read as “1”. 1.8 -40 °C 25 °C 85 °C 105 °C 1.7 1.6 Vthreshold [V] 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 37-202. I/O pin input threshold voltage vs. VCC. VIL I/O pin read as “0”. 1.75 -40 °C 25 °C 85 °C 105 °C 1.60 1.45 Vthreshold [V] 1.30 1.15 1.00 0.85 0.70 0.55 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
Figure 37-203. I/O pin input hysteresis vs. VCC. 0.32 0.29 0.26 Vthreshold [V] 0.23 25 °C 0.20 0.17 -40 °C 85 °C 0.14 0.11 105 °C 0.08 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 37.3.3 ADC Characteristics Figure 37-204. INL error vs. external VREF. T = 25°C, VCC = 3.6V, external reference. 2.7 2.4 Single-ended unsigned mode 2.1 INL [LSB] 1.8 1.5 1.2 Dif f erential mode 0.9 0.6 0.3 Single-ended signed mode 0.0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.
Figure 37-205. INL error vs. sample rate. T = 25°C, VCC = 2.7V, VREF = 1.0V external. 1.6 1.4 Single-ended signed mode 1.2 INL [LSB] 1.0 0.8 Dif f erential mode 0.6 Single-ended signed mode 0.4 0.2 0.0 500 650 800 950 1100 1250 1400 1550 1700 1850 2000 ADC sample rate [kSps] Figure 37-206. INL error vs. input code 2.0 1.5 1.0 INL [LSB] 0.5 0.0 -0.5 -1.0 -1.5 -2.
Figure 37-207. DNL error vs. external VREF. T = 25°C, VCC = 3.6V, external reference. 1.1 1.0 Single-ended unsigned mode 0.9 DNL [LSB] 0.8 0.7 0.6 Dif f erential mode 0.5 0.4 Single-ended signed mode 0.3 0.2 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 Vref [V] Figure 37-208. DNL error vs. sample rate. T = 25°C, VCC = 2.7V, VREF = 1.0V external. 0.43 0.41 Single-ended unsigned mode 0.38 DNL [LSB] 0.36 Dif f erential mode 0.33 0.31 0.28 0.26 Single-ended signed mode 0.
Figure 37-209. DNL error vs. input code. 1.0 0.8 0.6 0.4 DNL [LSB] 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096 ADC input code Figure 37-210. Gain error vs. VREF. T = 25°C, VCC = 3.6V, ADC sampling speed = 500ksps. 12 Gain Error [mV] 10 Single-ended signed mode 8 Single-ended unsigned mode 6 4 2 Dif f erential mode 0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.
Figure 37-211. Gain error vs. VCC. T = 25°C, VREF = external 1.0V, ADC sampling speed = 500ksps. 7 6 Single-ended signed mode Gain Error [mV] 5 4 Single-ended unsigned mode 3 2 Dif f erential mode 1 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 2.6 2.8 3.0 Vcc [V] Figure 37-212. Offset error vs. VREF. T = 25°C, VCC = 3.6V, ADC sampling speed = 500ksps. -1.0 -1.1 -1.1 Offset Error [mV] -1.2 -1.2 Dif f erential mode -1.3 -1.3 -1.4 -1.4 -1.5 -1.5 1.0 1.2 1.4 1.6 1.8 2.0 2.
Figure 37-213. Gain error vs. temperature. VCC = 2.7V, VREF = external 1.0V. 8 7 Single-ended signed mode Gain Error [mV] 6 5 4 Single-ended unsigned mode 3 2 Dif f erential mode 1 0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [oC] Figure 37-214. Offset error vs. VCC. T = 25°C, VREF = external 1.0V, ADC sampling speed = 500ksps. -0.3 -0.4 Offset Error [mV] -0.5 Dif f erential mode -0.6 -0.7 -0.8 -0.9 -1.0 -1.1 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.
Figure 37-215. Noise vs. VREF. T = 25°C, VCC = 3.6V, ADC sampling speed = 500ksps. 0.9 Single-ended signed mode 0.8 Noise [mV RMS] 0.7 0.6 Single-ended unsigend mode 0.5 0.4 0.3 Dif f erential mode 0.2 0.1 0.0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 Vref [V] Figure 37-216. Noise vs. VCC. T = 25°C, VREF = external 1.0V, ADC sampling speed = 500ksps. 0.8 Single-ended signed mode 0.7 Noise [mV RMS] 0.6 0.5 Single-ended unsigned mode 0.4 0.
37.3.4 DAC Characteristics Figure 37-217. DAC INL error vs. VREF. VCC = 3.6V. 2.4 2.1 DACINL [LSB] 1.8 1.5 - 40°C 25°C 85°C 105°C 1.2 0.9 0.6 0.3 0.0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 Vref [V] Figure 37-218. DNL error vs. VREF. VCC = 3.6V. 1.8 1.6 1.4 DAC DNL [LSB] 1.2 1.0 0.8 - 40°C 0.6 25°C 85°C 105°C 0.4 0.2 0.0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.
Figure 37-219. DAC noise vs. temperature. VCC = 2.7V, VREF = 1.0V . 0.178 0.176 0.174 Noise[mV RMS] 0.172 0.170 0.168 0.166 0.164 0.162 0.160 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [oC] 37.3.5 Analog Comparator Characteristics Figure 37-220. Analog comparator hysteresis vs. VCC. High-speed, small hysteresis. 25 24 105°C 23 85°C VHYST [mV] 22 25°C 21 20 19 - 40°C 18 17 16 15 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
Figure 37-221. Analog comparator hysteresis vs. VCC. Low power, small hysteresis. 36 105°C 85°C 34 VHYST [mV] 32 30 25°C 28 - 40°C 26 24 22 20 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 37-222. Analog comparator hysteresis vs. VCC. High-speed mode, large hysteresis. 47 105°C 85°C 45 43 25°C VHYST [mV] 41 39 - 40°C 37 35 33 31 29 27 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
Figure 37-223. Analog comparator hysteresis vs. VCC. Low power, large hysteresis. 76 105°C 85°C 73 70 67 VHYST [mV] 64 25°C 61 58 55 - 40°C 52 49 46 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 37-224. Analog comparator current source vs. calibration value. Temperature = 25°C. 8 ICURRENTSOURCE [µA] 7 6 5 3.6V 3.0V 2.7V 2.2V 1.8V 1.6V 4 3 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CURRCALIBA[3..
Figure 37-225. Analog comparator current source vs. calibration value. VCC = 3.0V. 7.2 6.8 ICURRENTSOURCE [uA] 6.4 6.0 5.6 5.2 4.8 4.4 - 40°C 25°C 85°C 105°C 4.0 3.6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CURRCALIBA[3..0] Figure 37-226. Voltage scaler INL vs. SCALEFAC. T = 25°C, VCC = 3.0V. 0.15 0.12 0.09 INL [LSB] 0.06 0.03 0.00 -0.03 -0.06 -0.09 -0.12 -0.
37.3.6 Internal 1.0V reference Characteristics Figure 37-227. ADC/DAC Internal 1.0V reference vs. temperature. 1.004 1.6 V 1.8 V 2.2 V 2.7 V 3.0 V 3.6 V Bandgap Voltage [V] 1.002 1.000 0.998 0.996 0.994 0.992 -45 -30 -15 0 15 30 45 60 75 90 105 Temperature [°C] 37.3.7 BOD Characteristics Figure 37-228. BOD thresholds vs. temperature. BOD level = 1.6V. 1.644 1.641 1.638 Rising Vcc VBOT [V] 1.635 1.632 Falling Vcc 1.629 1.626 1.623 1.620 1.
Figure 37-229. BOD thresholds vs. temperature. BOD level = 3.0V. 3.08 3.07 Rising Vcc 3.06 VBOT [V] 3.05 3.04 3.03 Falling Vcc 3.02 3.01 3.00 -45 -30 -15 0 15 30 45 60 75 90 105 Temperature [°C] 37.3.8 External Reset Characteristics Figure 37-230. Minimum Reset pin pulse width vs. VCC. 135 130 125 tRST [ns] 120 115 110 105 100 105°C 85°C 95 90 25°C - 40°C 85 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
Figure 37-231. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 1.8V. 80 70 IRESET [µA] 60 50 40 30 - 40°C 25°C 85°C 105°C 20 10 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VRESET [V] Figure 37-232. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.0V. 120 105 IRESET [µA] 90 75 60 45 30 - 40°C 25°C 85°C 105°C 15 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.
Figure 37-233. Reset pin pull-up resistor current vs. reset pin voltage. VCC = 3.3V. 150 135 120 IRESET [µA] 105 90 75 60 45 - 40°C 25°C 85°C 105°C 30 15 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 VRESET [V] Figure 37-234. Reset pin input threshold voltage vs. VCC. VIH - Reset pin read as “1”. 2.2 - 40°C 25°C 85°C 105°C 2.1 VTHRESHOLD [V] 1.9 1.8 1.6 1.5 1.3 1.2 1.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
Figure 37-235. Reset pin input threshold voltage vs. VCC. VIL - Reset pin read as “0”. 1.75 - 40°C 25°C 85°C 105°C 1.60 VTHRESHOLD [V] 1.45 1.30 1.15 1.00 0.85 0.70 0.55 0.40 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 37.3.9 Power-on Reset Characteristics Figure 37-236. Power-on reset current consumption vs. VCC. BOD level = 3.0V, enabled in continuous mode. 300 105°C 85°C 25°C - 40°C 250 I CC [µA] 200 150 100 50 0 0.4 0.7 1.0 1.3 1.6 1.9 2.2 2.5 2.
Figure 37-237. Power-on reset current consumption vs. VCC. BOD level = 3.0V, enabled in sampled mode. 300 105°C 250 I CC [µA] 200 85°C 25°C - 40°C 150 100 50 0 0.4 0.7 1.0 1.3 1.6 1.9 2.2 2.5 2.8 VCC [V] 37.3.10 Oscillator Characteristics 37.3.10.1 Ultra Low-Power internal oscillator Figure 37-238. Ultra Low-Power internal oscillator frequency vs. temperature. 34.0 33.7 Frequency [kHz] 33.4 33.1 32.8 32.5 32.2 31.9 3.6 V 3.0 V 2.7 V 2.2 V 1.8 V 1.6 V 31.6 31.3 31.
37.3.10.2 32.768kHz Internal Oscillator Figure 37-239. 32.768kHz internal oscillator frequency vs. temperature. 32.85 3.6 V 3.0 V 2.7 V 2.2 V 1.8 V 1.6 V 32.82 32.79 Frequency [kHz] 32.76 32.73 32.70 32.67 32.64 32.61 32.58 32.55 -45 -30 -15 0 15 30 45 60 75 90 105 Temperature [°C] Figure 37-240. 32.768kHz internal oscillator frequency vs. calibration value. VCC = 3.0V, T = 25°C. 53 50 Frequency [kHz] 47 44 41 38 35 32 29 26 23 0 30 60 90 120 150 180 210 240 270 RC32KCAL[7..
37.3.10.3 2MHz Internal Oscillator Figure 37-241. 2MHz internal oscillator frequency vs. temperature. DFLL disabled. 2.12 2.10 Frequency [MHz] 2.08 2.06 2.04 2.02 3.6 V 3.0 V 2.7 V 2.2 V 1.8 V 1.6 V 2.00 1.98 1.96 1.94 -45 -30 -15 0 15 30 45 60 75 90 105 Temperature [°C] Figure 37-242. 2MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator . 2.010 3.6 V 1.8 V 2.2 V 3.0 V 1.6 V 2.7 V 2.008 2.006 Frequency [MHz] 2.004 2.002 2.000 1.998 1.
Figure 37-243. 2MHz internal oscillator CALA calibration step size. VCC = 3V. 0.28 % Frequency Step size [%] 0.26 % 0.24 % 0.22 % 0.20 % - 40°C 25°C 105°C 85°C 0.18 % 0.16 % 0.14 % 0.12 % 0 16 32 48 64 80 96 112 128 CALA 37.3.10.4 32MHz Internal Oscillator Figure 37-244. 32MHz internal oscillator frequency vs. temperature. DFLL disabled. 35.5 35.0 Frequency [MHz] 34.5 34.0 33.5 33.0 3.6 V 3.0 V 2.7 V 2.2 V 1.8 V 1.6 V 32.5 32.0 31.5 31.
Figure 37-245. 32MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 32.12 32.08 Frequency [MHz] 32.04 32.00 3.6 V 31.96 31.92 31.88 31.84 3.0 V 2.7 V 2.2 V 1.8 V 1.6 V 31.80 -45 -30 -15 0 15 30 45 60 75 90 105 Temperature [°C] Figure 37-246. 32MHz internal oscillator CALA calibration step size. VCC = 3.0V. 0.34 % Frequency Step size[%] 0.31 % 0.28 % - 40°C 0.25 % 0.22 % 0.19 % 0.16 % 85°C 105°C 0.13 % 25°C 0.
Figure 37-247. 32MHz internal oscillator CALB calibration step size. VCC = 3.0V 2.80 % Frequency Step size [%] 2.60 % 2.40 % 2.20 % 2.00 % 1.80 % 1.60 % 1.40 % - 40°C 25°C 85°C 105°C 1.20 % 1.00 % 0.80 % 0 8 16 24 32 40 48 56 64 CALB 37.3.10.5 32MHz internal oscillator calibrated to 48MHz Figure 37-248. 48MHz internal oscillator frequency vs. temperature. DFLL disabled. 53.4 52.6 Frequency[MHz] 51.8 51.0 50.2 49.4 48.6 3.6 V 3.0 V 2.7 V 2.2 V 1.8 V 1.6 V 47.8 47.0 46.
Figure 37-249. 48MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 48.15 3.6 V 48.10 3.0 V 2.7 V 2.2 V 1.8 V 1.6 V 48.05 Frequency[MHz] 48.00 47.95 47.90 47.85 47.80 47.75 47.70 -45 -30 -15 0 15 30 45 60 75 90 105 Temperature [°C] Figure 37-250. 48MHz internal oscillator CALA calibration step size. VCC = 3.0V 0.30 % Frequency Step size [%] 0.28 % 0.26 % 0.24 % 0.22 % - 40°C 0.20 % 0.18 % 105°C 25°C 85°C 0.16 % 0.14 % 0.12 % 0.
37.3.11 Two-Wire Interface characteristics Figure 37-251. SDA hold time vs. supply voltage. 300 295 290 Holdtime [ns] 285 105°C 280 85°C 275 270 25°C 265 - 40°C 260 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 Vcc [V] 37.3.12 PDI characteristics Figure 37-252. Maximum PDI frequency vs. VCC. 30 - Maximum Frequency [MHz] 28 26 24 - 40°C 22 85°C 25°C 20 105°C 18 16 14 12 10 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
37.4 ATxmega128A4U 37.4.1 Current consumption 37.4.1.1 Active mode supply current Figure 37-253. Active supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C. 800 3.6V 700 600 Icc [µA] 3.0V 500 2.7V 400 2.2V 300 1.8V 1.6V 200 100 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 37-254. Active supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C. 13.5 12.0 3.6V Icc [mA] 10.5 3.0V 9.0 2.7V 7.5 6.0 4.5 2.2V 3.0 1.8V 1.
Figure 37-255. Active mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator IccVcc [uA] 270 240 - 40 °C 210 25 °C 180 85 °C 105 °C 150 120 90 60 30 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 37-256. Active mode supply current vs. VCC. fSYS = 1MHz external clock. 800 -40 °C 25 °C 85 °C 105 °C 700 600 Icc [uA] 500 400 300 200 100 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
Figure 37-257. Active mode supply current vs. VCC. fSYS = 2MHz internal oscillator -40 °C 25 °C 85 °C 105 °C 1400 1225 1050 Icc [uA] 875 700 525 350 175 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Vcc [V] Figure 37-258. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz. 5800 -40 °C 25 °C 85 °C 105 °C 5200 4600 Icc [uA] 4000 3400 2800 2200 1600 1000 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
Figure 37-259. Active mode supply current vs. VCC. fSYS = 32MHz internal oscillator. 13.4 12.6 -40 °C 25 °C 85 °C 105 °C 11.8 Icc [mA] 11.0 10.2 9.4 8.6 7.8 7.0 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] 37.4.1.2 Idle mode supply current Figure 37-260. Idle mode supply current vs. frequency. fSYS = 0 - 1MHz external clock, T = 25°C 160 3.6 V Icc [µA] 140 120 3.0 V 100 2.7 V 80 2.2 V 60 1.8 V 1.6 V 40 20 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 37-261. Idle mode supply current vs. frequency. fSYS = 1 - 32MHz external clock, T = 25°C 5.4 3.6V 4.8 4.2 3.0V Icc [mA] 3.6 2.7V 3.0 2.4 1.8 2.2V 1.2 1.8V 0.6 0 0 4 8 12 16 20 24 28 32 Frenquecy [MHz] Figure 37-262. Idle mode supply current vs. VCC. fSYS = 32.768kHz internal oscillator. 38 105 °C 37 36 35 -40 °C Icc [uA] 34 85 °C 33 25 °C 32 31 30 29 28 27 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
Figure 37-263. Idle mode supply current vs. VCC. fSYS = 1MHz external clock 160 105 °C 85 °C 25 °C -40 °C 150 140 130 Icc[uA] 120 110 100 90 80 70 60 50 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 37-264. Idle mode supply current vs. VCC. fSYS = 2MHz internal oscillator 105 °C 85 °C 25 °C -40 °C 330 310 290 270 Icc [uA] 250 230 210 190 170 150 130 110 90 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
Figure 37-265. Idle mode supply current vs. VCC. fSYS = 32MHz internal oscillator prescaled to 8MHz 2000 -40 °C 25 °C 85 °C 105 °C 1800 Icc [uA] 1600 1400 1200 1000 800 600 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 Vcc [V] Figure 37-266. Idle mode current vs. VCC. fSYS = 32MHz internal oscillator 5000 -40 °C 25 °C 85 °C 105 °C 4750 4500 Icc [uA] 4250 4000 3750 3500 3250 3000 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.
37.4.1.3 Power-down mode supply current Figure 37-267. Power-down mode supply current vs. temperature. All functions disabled 5.0 3.6 V 4.5 3.0 V 2.7 V 2.2 V 1.8 V 1.6 V 4.0 3.5 Icc [uA] 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 37-268. Power-down mode supply current vs. VCC. All functions disabled 5.0 105 °C 4.5 4.0 3.5 Icc [uA] 3.0 2.5 2.0 85 °C 1.5 1.0 0.5 25 °C -40 °C 0.0 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.
Figure 37-269. Power-down mode supply current vs. VCC. Watchdog and sampled BOD enabled 7.3 105 °C 6.8 6.3 5.8 5.3 Icc [uA] 4.8 4.3 3.8 3.3 85 °C 2.8 2.3 1.8 1.3 25 °C -40 °C 0.8 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 Vcc [V] 37.4.1.4 Power-save mode supply current Figure 37-270. Power-save mode supply current vs.VCC. Real Time Counter enabled and running from 1.024kHz output of 32.768kHz TOSC. 0.9 Normal mode 0.8 0.7 ICC [µA] 0.6 Low-power mode 0.5 0.4 0.3 0.2 0.1 0 1.6 1.8 2.
37.4.1.5 Standby mode supply current Figure 37-271. Standby supply current vs. VCC. Standby, fSYS = 1MHz 12.5 105 °C 11.5 10.5 9.5 85 °C ICC [uA] 8.5 25 °C -40 °C 7.5 6.5 5.5 4.5 3.5 2.5 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-272. Standby supply current vs. VCC. T = 25°C, running from different crystal oscillators 480 16MHz 12MHz 440 ICC [µA] 400 360 320 8MHz 2MHz 280 240 0.454MHz 200 160 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
37.4.2 I/O Pin Characteristics 37.4.2.1 Pull-up Figure 37-273. I/O pin pull-up resistor current vs. input voltage. VCC = 1.8V 72 64 56 I [uA] 48 40 32 24 16 -40 °C 25 °C 85 °C 105 °C 8 0 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 Vpin [V] Figure 37-274. I/O pin pull-up resistor current vs. input voltage. VCC = 3.0V 120 105 90 I [uA] 75 60 45 30 -40 °C 25 °C 85 °C 105 °C 15 0 0.1 0.4 0.7 1.0 1.3 1.6 1.9 2.2 2.5 2.8 3.
Figure 37-275. I/O pin pull-up resistor current vs. input voltage. VCC = 3.3V. 135 120 105 I [uA] 90 75 60 45 30 -40 °C 25 °C 85 °C 105 °C 15 0 0.1 0.4 0.7 1.0 1.3 1.6 1.9 2.2 2.5 2.8 3.1 3.4 Vpin [V] 37.4.2.2 Output Voltage vs. Sink/Source Current Figure 37-276. I/O pin output voltage vs. source current. VCC = 1.8V 1.9 1.8 1.7 1.6 1.5 Vpin [V] 1.4 1.3 1.2 1.1 1.0 -40 °C 0.9 105 °C 85 °C 25 °C 0.8 0.7 0.6 0.
Figure 37-277. I/O pin output voltage vs. source current. VCC = 3.0V 3.30 2.95 2.60 Vpin [V] 2.25 1.90 1.55 -40 °C 25 °C 85 °C -24 -21 105 °C 1.20 0.85 0.50 -30 -27 -18 -15 -12 -9 -6 -3 0 -12 -9 -6 -3 0 Ipin [mA] Figure 37-278. I/O pin output voltage vs. source current. VCC = 3.3V 3.5 3.2 2.9 Vpin [V] 2.6 2.3 2.0 1.7 -40 °C 1.4 25 °C 1.1 85 °C 0.8 105 °C 0.
Figure 37-279. I/O pin output voltage vs. source current 3.65 3.6 V 3.30 3.3 V 2.95 3.0 V 2.7 V Vpin [V] 2.60 2.25 1.90 1.8 V 1.6 V 1.55 1.20 0.85 0.50 -24 -21 -18 -15 -12 -9 -6 -3 0 Ipin [mA] Figure 37-280. I/O pin output voltage vs. sink current. VCC = 1.8V 1.0 0.9 105 °C 0.8 85 °C Vpin [V] 0.7 25 °C -40 °C 0.6 0.5 0.4 0.3 0.2 0.1 0.
Figure 37-281. I/O pin output voltage vs. sink current. VCC = 3.0V 1.1 105 °C 85 °C 1.0 0.9 25 °C -40 °C 0.8 Vpin [V] 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 3 6 9 12 15 18 21 24 27 30 Ipin [mA] Figure 37-282. I/O pin output voltage vs. sink current. VCC = 3.3V 105 °C 85 °C 1.0 Vpin [V] 0.9 0.8 25 °C 0.7 -40 °C 0.6 0.5 0.4 0.3 0.2 0.1 0.
Figure 37-283. I/O pin output voltage vs. sink current 1.50 1.35 1.20 1.8 V 1.05 2.7 V 3.0 V 3.3 V 3.6 V Vpin [V] 1.6 V 0.90 0.75 0.60 0.45 0.30 0.15 0.00 0 3 6 9 12 15 18 21 24 27 30 Ipin [mA] 37.4.2.3 Thresholds and Hysteresis Figure 37-284. I/O pin input threshold voltage vs. VCC. T = 25°C 1.8 VIH 1.6 VIL Vthreshold [V] 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
Figure 37-285. I/O pin input threshold voltage vs. VCC. VIH I/O pin read as “1” 105 °C 85 °C 25 °C -40 °C 1.8 1.7 1.6 Vthreshold [V] 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 Vcc [V] Figure 37-286. I/O pin input threshold voltage vs. VCC. VIL I/O pin read as “0” 1.75 105 °C 85 °C 25 °C -40 °C 1.60 1.45 Vthreshold [V] 1.30 1.15 1.00 0.85 0.70 0.55 0.40 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
Figure 37-287. I/O pin input hysteresis vs. VCC 0.41 0.39 0.37 0.35 Vthreshold [V] 0.33 -40 °C 0.31 25 °C 0.29 0.27 0.25 85 °C 0.23 0.21 0.19 105 °C 0.17 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 Vcc [V] 37.4.3 ADC Characteristics Figure 37-288. INL error vs. external VREF T = 25°C, VCC = 3.6V, external reference 1.8 1.7 1.6 Differential Signed INL [LSB] 1.5 Single-ended Unsigned 1.4 1.3 1.2 1.1 1 0.9 Single-ended Signed 0.8 0.7 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.
Figure 37-289. INL error vs. sample rate T = 25°C, VCC = 3.6V, VREF = 3.0V external 1.4 1.35 1.3 Differential Mode INL [LSB] 1.25 1.2 Single-ended Unsigned 1.15 1.1 1.05 Single-ended Signed 1 0.95 0.9 500 650 800 950 1100 1250 1400 1550 1700 1850 2000 ADC Sample Rate [kSPS] Figure 37-290. INL error vs. input code 2.0 1.5 INL [LSB] 1.0 0.5 0 -0.5 -1.0 -1.5 -2.
Figure 37-291. DNL error vs. external VREF T = 25°C, VCC = 3.6V, external reference 0.9 0.88 0.86 DNL [LSB] Differential Mode 0.84 Single-ended Signed 0.82 0.8 0.78 Single-ended Unsigned 0.76 0.74 0.72 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 VREF [V] Figure 37-292. DNL error vs. sample rate T = 25°C, VCC = 3.6V, VREF = 3.0V external 0.9 0.89 Differential Signed 0.88 DNL [LSB] 0.87 0.86 0.85 Single-ended Signed 0.84 0.83 0.82 0.81 Single-ended Unsigned 0.8 0.
Figure 37-293. DNL error vs. input code 0.8 0.6 DNL [LSB] 0.4 0.2 0 -0.2 -0.4 -0.6 0 512 1024 1536 2048 2560 3072 3584 4096 ADC Input Code Figure 37-294. Gain error vs. VREF T = 25°C, VCC = 3.6V, ADC sampling speed = 500ksps 3 Single-ended Signed Gain Error [mV] 2 1 Differential Mode 0 -1 Single-ended Unsigned -2 -3 -4 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.
Figure 37-295. Gain error vs. VCC T = 25°C, VREF = external 1.0V, ADC sampling speed = 500ksps 2.2 1.9 Single-ended Signed Gain Error [mV] 1.6 1.3 Differential Mode 1 0.7 0.4 Single-ended Unsigned 0.1 -0.2 -0.5 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 37-296. Offset error vs. VREF T = 25°C, VCC = 3.6V, ADC sampling speed = 500ksps -1 Offset Error [mV] -1.1 -1.2 -1.3 -1.4 -1.5 Differential Mode -1.6 -1.7 -1.8 -1.9 -2 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.
Figure 37-297. Gain error vs. temperature VCC = 3.0V, VREF = external 2.0V 3 2 Gain Error [mV] Single-ended Signed 1 Differential Signed 0 -1 Single-ended Unsigned -2 -3 -4 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [ºC] Figure 37-298. Offset error vs. VCC T = 25°C, VREF = external 1.0V, ADC sampling speed = 500ksps -0.3 -0.4 Offset Error [mV] -0.5 -0.6 -0.7 Differential Signed -0.8 -0.9 -1 -1.1 -1.2 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.
Figure 37-299. Noise vs. VREF T = 25°C, VCC = 3.6V, ADC sampling speed = 500ksps 1.3 Single-ended Signed Noise [mV RMS] 1.15 Single-ended Unsigned 1 0.85 0.7 0.55 Differential Signed 0.4 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 VREF [V] Figure 37-300. Noise vs. VCC T = 25°C, VREF = external 1.0V, ADC sampling speed = 500ksps 1.3 1.2 Single-ended Signed Noise [mV RMS] 1.1 1 0.9 0.8 Single-ended Unsigned 0.7 0.6 0.5 Differential Signed 0.4 0.3 1.6 1.8 2 2.2 2.4 2.6 2.
37.4.4 DAC Characteristics Figure 37-301. DAC INL error vs. VREF VCC = 3.6V 1.9 1.8 INL [LSB] 1.7 1.6 1.5 1.4 1.3 1.2 25°C 1.1 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] Figure 37-302. DNL error vs. VREF. T = 25°C, VCC = 3.6V. 0.9 DNL [LSB] 0.85 0.8 0.75 0.7 0.65 25ºC 0.6 1.6 1.8 2 2.2 2.4 2.6 2.
Figure 37-303. DAC noise vs. temperature VCC = 3.0V, VREF = 2.4V 0.185 0.180 Noise [mV RMS] 0.175 0.170 0.165 0.160 0.155 0.150 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [ºC] 37.4.5 Analog Comparator Characteristics Figure 37-304. Analog comparator hysteresis vs. VCC. High-speed, small hysteresis 14 13 105°C 12 85°C VHYST [mV] 11 10 25°C 9 8 7 -40° 6 5 4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
Figure 37-305. Analog comparator hysteresis vs. VCC. Low power, small hysteresis 30 28 105°C 85°C 26 24 VHYST [mV] 25°C 22 -40°C 20 18 16 14 12 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 37-306. Analog comparator hysteresis vs. VCC. High-speed mode, large hysteresis 32 105°C 85°C 30 28 VHYST [mV] 26 25°C 24 22 -40°C 20 18 16 14 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
Figure 37-307. Analog comparator hysteresis vs. VCC. Low power, large hysteresis 68 64 105°C 85°C 60 VHYST [mV] 56 25°C 52 48 -40°C 44 40 36 32 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 37-308. Analog comparator current source vs. calibration value. Temperature = 25°C 8 7.5 ICURRENTSOURCE [µA] 7 6.5 6 5.5 5 4.5 3.6V 4 3.0V 3.5 3 2.2V 1.8V 2.5 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CURRCALIBA[3..
Figure 37-309. Analog comparator current source vs. calibration value. VCC = 3.0V. 7 ICURRENTSOURCE [µA] 6.5 6 5.5 5 4.5 -40°C 25°C 85°C 4 3.5 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CURRCALIBA[3..0] Figure 37-310. Voltage scaler INL vs. SCALEFAC. T = 25°C, VCC = 3.0V. 0.050 0.025 INL [LSB] 0 -0.025 -0.050 -0.075 -0.100 25°C -0.125 -0.
37.4.6 Internal 1.0V reference Characteristics Figure 37-311. ADC/DAC Internal 1.0V reference vs. temperature 1.0024 1.0020 1.6V 1.8V Bandgap Voltage [V] 1.0016 1.0012 1.0008 1.0004 1.0000 2.7V 3.0V 0.9996 0.9992 3.6V 0.9988 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature [°C] 37.4.7 BOD Characteristics Figure 37-312. BOD thresholds vs. temperature. BOD level = 1.6V 1.596 Rising Vcc 1.593 Vbot [V] 1.590 1.587 1.584 Falling Vcc 1.581 1.578 1.575 1.
Figure 37-313. BOD thresholds vs. temperature. BOD level = 3.0V 3.03 3.02 Rising Vcc 3.01 Vbot [V] 3.00 2.99 2.98 Falling Vcc 2.97 2.96 2.95 2.94 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] 37.4.8 External Reset Characteristics Figure 37-314. Minimum Reset pin pulse width vs. VCC 135 130 125 120 Trst [ns] 115 110 105 100 105 °C 85 °C 95 90 25 °C -40 °C 85 80 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
Figure 37-315. Reset pin pull-up resistor current vs. reset pin voltage VCC = 1.8V 80 72 64 Ireset [uA] 56 48 40 32 24 16 -40 °C 25 °C 85 °C 105 °C 8 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 Vreset [V] Figure 37-316. Reset pin pull-up resistor current vs. reset pin voltage VCC = 3.0V 135 120 105 Ireset [uA] 90 75 60 45 30 -40 °C 25 °C 85 °C 105 °C 15 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.
Figure 37-317. Reset pin pull-up resistor current vs. reset pin voltage VCC = 3.3V 150 135 120 Ireset [uA] 105 90 75 60 45 30 -40 °C 25 °C 85 °C 105 °C 15 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 Vreset [V] Figure 37-318. Reset pin input threshold voltage vs. VCC VIH - Reset pin read as “1” 2.20 -40 °C 25 °C 85 °C 105 °C 2.05 Vthreshold [V] 1.90 1.75 1.60 1.45 1.30 1.15 1.00 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
Figure 37-319. Reset pin input threshold voltage vs. VCC VIL - Reset pin read as “0” 1.8 105 °C 85 °C 25 °C -40 °C 1.6 VTHRESHOLD [V] 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 37.4.9 Power-on Reset Characteristics Figure 37-320. Power-on reset current consumption vs. VCC BOD level = 3.0V, enabled in continuous mode ICC [µA] 700 -40 °C 600 25 °C 500 85 °C 105 °C 400 300 200 100 0 0.4 0.7 1.0 1.3 1.6 1.9 2.2 2.5 2.
Figure 37-321. Power-on reset current consumption vs. VCC BOD level = 3.0V, enabled in sampled mode 650 -40 °C 585 520 25 °C ICC [µA] 455 85 ° °C 105°°C 390 325 260 195 130 65 0 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 VCC [V] 37.4.10 Oscillator Characteristics 37.4.10.1 Ultra Low-Power internal oscillator Figure 37-322. Ultra Low-Power internal oscillator frequency vs. temperature. 33.75 33.50 33.25 Frequency [kHz] 33.00 32.75 32.50 32.25 32.00 3.6 V 3.3 V 3.0 V 2.7 V 1.8 V 1.6 V 31.75 31.
37.4.10.2 32.768kHz Internal Oscillator Figure 37-323. 32.768kHz internal oscillator frequency vs. temperature 32.82 3.6 V 3.3 V 3.0 V 2.7 V 2.2 V 1.8 V 32.79 32.76 Frequency [kHz] 32.73 32.70 32.67 32.64 32.61 32.58 32.55 32.52 32.49 32.46 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature [°C] Figure 37-324. 32.768kHz internal oscillator frequency vs. calibration value VCC = 3.0V, T = 25°C 52 3.
37.4.10.3 2MHz Internal Oscillator Figure 37-325. 2MHz internal oscillator frequency vs. temperature DFLL disabled 2.16 2.14 2.12 Frequency [MHz] 2.10 2.08 2.06 2.04 3.6 V 3.3 V 3.0 V 2.7 V 2.2 V 1.8 V 2.02 2.00 1.98 1.96 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature [°C] Figure 37-326. 2MHz internal oscillator frequency vs. temperature DFLL enabled, from the 32.768kHz internal oscillator 2.006 3.6 V 3.3 V 3.0 V 2.7 V 2.2 V 1.8 V 2.004 2.002 Frequency [MHz] 2.000 1.
Figure 37-327. 2MHz internal oscillator CALA calibration step size VCC = 3V 0.30 0.28 Step Size [%] 0.26 0.24 0.22 0.20 -40 °C 0.18 25 °C 0.16 85 °C 105 °C 0.14 0 10 20 30 40 50 60 70 80 90 100 110 120 130 CALA 37.4.10.4 32MHz Internal Oscillator Figure 37-328. 32MHz internal oscillator frequency vs. temperature DFLL disabled 36.00 35.55 35.10 Frequency [MHz] 34.65 34.20 33.75 33.30 32.85 3.6 V 3.3 V 3.0 V 2.7 V 2.2 V 1.8 V 32.40 31.95 31.50 31.
Figure 37-329. 32MHz internal oscillator frequency vs. temperature DFLL enabled, from the 32.768kHz internal oscillator 32.05 1.8 V 2.2 V 2.7 V 3.0 V 3.3 V 3.6 V 32.02 31.99 Frequency [MHz] 31.96 31.93 31.90 31.87 31.84 31.81 31.78 31.75 31.72 31.69 31.66 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature [°C] Figure 37-330. 32MHz internal oscillator CALA calibration step size VCC = 3.0V 0.32 0.29 Step Size [%] 0.26 0.23 -40 °C 0.20 105 °C 85 °C 25 °C 0.17 0.
37.4.10.5 32MHz internal oscillator calibrated to 48MHz Figure 37-331. 48MHz internal oscillator frequency vs. temperature DFLL disabled 53.9 53.2 52.5 Frequency [MHz] 51.8 51.1 50.4 49.7 49.0 3.6 V 3.3 V 3.0 V 48.3 47.6 2.7 V 2.2 V 1.8 V 46.9 46.2 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature [°C] Figure 37-332. 48MHz internal oscillator frequency vs. temperature DFLL enabled, from the 32.768kHz internal oscillator 48.3 1.8 V 2.2 V 2.7 V 3.0 V 3.3 V 3.6 V 48.
Figure 37-333. 48MHz internal oscillator CALA calibration step size VCC = 3V 0.28 0.26 Step Size [%] 0.24 0.22 0.2 -40 °C 0.18 105 °C 85 °C 25 °C 0.16 0.14 0 10 20 30 40 50 60 70 80 90 100 110 120 130 CALA 37.4.11 Two-Wire Interface characteristics Figure 37-334. SDA hold time vs. supply voltage 300 295 290 Holdtime [ns] 285 105°C 280 85°C 275 270 25°C 265 - 40°C 260 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.
37.4.12 PDI characteristics Figure 37-335. Maximum PDI frequency vs. VCC -40 °C 25 °C 85 °C 105 °C 31 Frequency max [MHz] 28 25 22 19 16 13 10 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.
38. Errata 38.1 ATxmega16A4U 38.1.1 Rev. E z ADC may have missing codes in SE unsigned mode at low temp and low Vcc z CRC fails for Range CRC when end address is the last word address of a flash section z AWeX fault protection restore is not done correct in Pattern Generation Mode 1. ADC may have missing codes in SE unsigned mode at low temp and low Vcc The ADC may have missing codes i single ended (SE) unsigned mode below 0C when Vcc is below 1.8V. Problem fix/Workaround Use the ADC in SE signed mode.
38.2 ATxmega32A4U 38.2.1 Rev. E z ADC may have missing codes in SE unsigned mode at low temp and low Vcc z CRC fails for Range CRC when end address is the last word address of a flash section z AWeX fault protection restore is not done correct in Pattern Generation Mode 1. ADC may have missing codes in SE unsigned mode at low temp and low Vcc The ADC may have missing codes i single ended (SE) unsigned mode below 0C when Vcc is below 1.8V. Problem fix/Workaround Use the ADC in SE signed mode. 2.
38.3 ATxmega64A4U 38.3.1 Rev. D z ADC may have missing codes in SE unsigned mode at low temp and low Vcc z CRC fails for Range CRC when end address is the last word address of a flash section 1. ADC may have missing codes in SE unsigned mode at low temp and low Vcc The ADC may have missing codes i single ended (SE) unsigned mode below 0C when Vcc is below 1.8V. Problem fix/Workaround Use the ADC in SE signed mode. 2.
3. AWeX fault protection restore is not done correct in Pattern Generation Mode When a fault is detected the OUTOVEN register is cleared, and when fault condition is cleared, OUTOVEN is restored according to the corresponding enabled DTI channels. For Common Waveform Channel Mode (CWCM), this has no effect as the OUTOVEN is correct after restoring from fault. For Pattern Generation Mode (PGM), OUTOVEN should instead have been restored according to the DTLSBUF register.
38.4 ATxmega128A4U 38.4.1 rev. A z ADC may have missing codes in SE unsigned mode at low temp and low Vcc 1. ADC may have missing codes in SE unsigned mode at low temp and low Vcc The ADC may have missing codes i single ended (SE) unsigned mode below 0C when Vcc is below 1.8V. Problem fix/Workaround Use the ADC in SE signed mode.
39. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 39.1 8387H –09/2014 1. Updated “Ordering Information” on page 2. Added ordering information for ATxmega16A4U/32A4U/64A4U/128A4U @ 105°C 2. Updated the Application Table Section from 4K/4K/4K/4K to 8K/4K/4K/4K in the Figure 7-1 on page 14 3.
39.5 8387D – 02/2013 1. Updated typos in “Ordering Information” on page 2. 2. Updated PE2 and PE3 pins in “Pinout/Block Diagram” on page 4 to indicate that these can be used as TOSC pins. 3. Renamed pin 19 from VDD to VCC in Figure 2-1 on page 4. 4. Updated page size for ATxmega128A4U in Table 7-3 on page 17. 5. Added column for TWI using external driver interface in Table 32-3 on page 59. 6. Updated ATxmega16A4U leakage current in Table 36-7 on page 77. 7.
5. Updated all typical characteristics in “Power-down mode supply current” on page 166. 6. Added electrical characteristics for “ATxmega32A4U” on page 93. 7. Added electrical characteristics for “ATxmega64A4U” on page 115. 8. Added electrical characteristics for “ATxmega128A4U” on page 137. 9. Added typical characteristics for “ATxmega64A4U” on page 243 10. Added typical characteristics for “ATxmega64A4U” on page 243. 12. Added typical characteristics for “ATxmega128A4U” on page 285. 13.
Table of Contents 1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Pinout/Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 4. Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.2 11.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 12. System Control and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 12.1 12.2 12.3 12.4 Features . . . . . . . . . . . . . . . . . . . . . . . . .
23.1 23.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 24. USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 24.1 24.2 Features . . . . . . . . . . . . . . . . . . . . .
37. Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 37.1 37.2 37.3 37.4 ATxmega16A4U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ATxmega32A4U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ATxmega64A4U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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