Datasheet

 2018 Microchip Technology Inc. Data Sheet Complete DS40002058A-page 98
ATxmega128A1U/ATxmega64A1U
37.1.15 SPI Characteristics
Figure 37-5. SPI timing requirements in master mode.
Figure 37-6. SPI timing requirements in slave mode.
MSB LSB
BSLBSM
t
MOS
t
MIS
t
MIH
t
SCKW
t
SCK
t
MOH
t
MOH
t
SCKF
t
SCKR
t
SCKW
MOSI
(Data Output)
MISO
(Data Input)
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS
MSB
LSB
BSLBSM
t
SIS
t
SIH
t
SSCKW
t
SSCKW
t
SSCK
t
SSH
t
SOSSH
t
SCKR
t
SCKF
t
SOS
t
SSS
t
SOSSS
MISO
(Data Output)
MOSI
(Data Input)
SCK
(CPOL = 1)
SCK
(CPOL = 0)
SS