Datasheet

92
ATtiny25/45/85 [DATASHEET]
2586Q–AVR–08/2013
to the OCR1B value. A software write that sets TCNT1 and OCR1B to the same value does not generate a com-
pare match.
A compare match will set the compare interrupt flag OCF1B after a synchronization delay following the compare
event.
12.3.6 OCR1C – Timer/Counter1 Output Compare RegisterC
The output compare register C is an 8-bit read/write register.
The Timer/Counter Output Compare Register C contains data to be continuously compared with Timer/Counter1.
A compare match does only occur if Timer/Counter1 counts to the OCR1C value. A software write that sets TCNT1
and OCR1C to the same value does not generate a compare match. If the CTC1 bit in TCCR1 is set, a compare
match will clear TCNT1.
This register has the same function in normal mode and PWM mode.
12.3.7 TIMSK – Timer/Counter Interrupt Mask Register
• Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero.
• Bit 6 – OCIE1A: Timer/Counter1 Output Compare Interrupt Enable
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare
MatchA, interrupt is enabled. The corresponding interrupt at vector $003 is executed if a compare matchA occurs.
The Compare Flag in Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register.
• Bit 5 – OCIE1B: Timer/Counter1 Output Compare Interrupt Enable
When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare
MatchB, interrupt is enabled. The corresponding interrupt at vector $009 is executed if a compare matchB occurs.
The Compare Flag in Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register.
• Bit 2 – TOIE1: Timer/Counter1 Overflow Interrupt Enable
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow inter-
rupt is enabled. The corresponding interrupt (at vector $004) is executed if an overflow in Timer/Counter1 occurs.
The Overflow Flag (Timer1) is set (one) in the Timer/Counter Interrupt Flag Register - TIFR.
• Bit 0 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero.
Bit 76543210
0x2D MSB LSB OCR1C
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 1 1 1 1 1 1 1 1
Bit 7 6 5 4 3 2 1 0
0x39 – OCIE1A OCIE1B
OCIE0A OCIE0B TOIE1 TOIE0 – TIMSK
Read/Write R R/W R/W R/W R/W R/W R/W R
Initial value 0 0 0 0 0 0 0 0