Datasheet

81
ATtiny25/45/85 [DATASHEET]
2586Q–AVR–08/2013
11.9.6 OCR0B – Output Compare Register B
The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value
(TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the
OC0B pin.
11.9.7 TIMSK – Timer/Counter Interrupt Mask Register
• Bits 7, 0 – Res: Reserved Bits
These bits are reserved bits and will always read as zero.
• Bit 4 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter0 Compare
Match A interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter0
occurs, i.e., when the OCF0A bit is set in the Timer/Counter 0 Interrupt Flag Register – TIFR0.
• Bit 3 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable
When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare
Match B interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter occurs,
i.e., when the OCF0B bit is set in the Timer/Counter Interrupt Flag Register – TIFR0.
• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter0 Overflow inter-
rupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the
TOV0 bit is set in the Timer/Counter 0 Interrupt Flag Register – TIFR0.
11.9.8 TIFR – Timer/Counter Interrupt Flag Register
• Bits 7, 0 – Res: Reserved Bits
These bits are reserved bits and will always read as zero.
• Bit 4 – OCF0A: Output Compare Flag 0 A
The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data in OCR0A – Out-
put Compare Register0. OCF0A is cleared by hardware when executing the corresponding interrupt handling
vector. Alternatively, OCF0A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0A
(Timer/Counter0 Compare Match Interrupt Enable), and OCF0A are set, the Timer/Counter0 Compare Match Inter-
rupt is executed.
Bit 76543210
0x28 OCR0B[7:0] OCR0B
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
0x39 –
OCIE1A OCIE1B OCIE0A OCIE0B TOIE1 TOIE0 – TIMSK
Read/Write R R/W R/W R/W R/W R/W R/W R
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
0x38 –
OCF1A OCF1B OCF0A OCF0B TOV1 TOV0 –TIFR
Read/Write R R/W R/W R/W R/W R/W R/W R
Initial Value00000000