Datasheet

69
ATtiny25/45/85 [DATASHEET]
2586Q–AVR–08/2013
be accessed by the CPU, regardless of whether clk
T0
is present or not. A CPU write overrides (has priority over) all
counter clear or count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in the Timer/Counter
Control Register (TCCR0A) and the WGM02 bit located in the Timer/Counter Control Register B (TCCR0B). There
are close connections between how the counter behaves (counts) and how waveforms are generated on the Out-
put Compare output OC0A. For more details about advanced counting sequences and waveform generation, see
“Modes of Operation” on page 71.
The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by the WGM0[1:0]
bits. TOV0 can be used for generating a CPU interrupt.
11.5 Output Compare Unit
The 8-bit comparator continuously compares TCNT0 with the Output Compare Registers (OCR0A and OCR0B).
Whenever TCNT0 equals OCR0A or OCR0B, the comparator signals a match. A match will set the Output Com-
pare Flag (OCF0A or OCF0B) at the next timer clock cycle. If the corresponding interrupt is enabled, the Output
Compare Flag generates an Output Compare interrupt. The Output Compare Flag is automatically cleared when
the interrupt is executed. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit loca-
tion. The Waveform Generator uses the match signal to generate an output according to operating mode set by the
WGM0[2:0] bits and Compare Output mode (COM0x[1:0]) bits. The max and bottom signals are used by the Wave-
form Generator for handling the special cases of the extreme values in some modes of operation (See “Modes of
Operation” on page 71.).
Figure 11-5 shows a block diagram of the Output Compare unit.
Figure 11-5. Output Compare Unit, Block Diagram
The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the
normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buff-
ering synchronizes the update of the OCR0x Compare Registers to either top or bottom of the counting sequence.
The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the
output glitch-free.
OCFnx (Int.Req.)
= (8-bit Comparator )
OCRnx
OCnx
DATA BUS
TCNTn
WGMn[1:0]
Waveform Generat or
top
FOCn
COMnX[1:0]
bottom